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author | Stephen Glancy <sglancy@us.ibm.com> | 2017-03-30 11:50:12 -0500 |
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committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-03-31 18:16:37 -0400 |
commit | 4ec5fe285a088a701f1071370720e7c04d2b6f7f (patch) | |
tree | e47d8365514e164a07bc6d4472f4a8c40fc40c4e /src/import/chips | |
parent | a36424c41b711c1361db33a9f2e2db2788fd91a9 (diff) | |
download | talos-hostboot-4ec5fe285a088a701f1071370720e7c04d2b6f7f.tar.gz talos-hostboot-4ec5fe285a088a701f1071370720e7c04d2b6f7f.zip |
Updates DCD to pass on a/b failure
The design team now recommends that both A-side and B-side failures
should not cause the part to fail IPL. We will now log the errors,
but proceed on with the calibration.
Also updates error messages to note that the algorithm recovered.
Change-Id: Ibef70d4222e25e7a268dfa6fa2c1d33de832be93
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38633
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38637
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C index d61b53432..4bea16d61 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C @@ -313,7 +313,8 @@ fapi_try_exit: /// @param[out] o_value - value to use for the DCD register /// @return FAPI2_RC_SUCCESS iff ok /// @note Due to DCD algorithm fails due to bad HW, the algorithm is going to do the following -/// 1) Return failing RC's if a and b both failed +/// Per the PHY team, we do not want to fail out existing HW for the DCD calibration fails +/// 1) Use prior calibrated value if a/b fail - return success /// 2) Use a if b failed /// 3) Use b if a failed /// 4) Average if a and b both passed @@ -328,16 +329,17 @@ fapi2::ReturnCode compute_dcd_value(fapi2::ReturnCode& io_a_side_rc, if(io_a_side_rc != FAPI2_RC_SUCCESS && io_b_side_rc != FAPI2_RC_SUCCESS) { // Log a-side, return b-side (chose this at random, but we want to exit) - FAPI_ERR("Both side A and side B failed, exiting with errors"); + FAPI_ERR("Recovered from DCD calibration fail - both side A and side B failed, using prior calibrated value"); fapi2::logError(io_a_side_rc); - return io_b_side_rc; + fapi2::logError(io_b_side_rc); + return FAPI2_RC_SUCCESS; } // 2) b failed, use a if(io_b_side_rc != FAPI2_RC_SUCCESS) { + FAPI_ERR("Recovered from DCD calibration fail - side B failed, using side-A's value"); fapi2::logError(io_b_side_rc); - FAPI_INF("Side B failed, using side-A's value"); o_value = i_a_side_val; return FAPI2_RC_SUCCESS; } @@ -345,14 +347,14 @@ fapi2::ReturnCode compute_dcd_value(fapi2::ReturnCode& io_a_side_rc, // 3) a failed, use b if(io_a_side_rc != FAPI2_RC_SUCCESS) { - FAPI_INF("Side A failed, using side-B's value"); + FAPI_ERR("Recovered from DCD calibration fail - side A failed, using side-B's value"); fapi2::logError(io_a_side_rc); o_value = i_b_side_val; return FAPI2_RC_SUCCESS; } // 4) average a and b as both passed - FAPI_INF("Both sides A/B passed - averaging"); + FAPI_DBG("Both sides A/B passed - averaging"); o_value = (i_a_side_val + i_b_side_val) / 2; return FAPI2_RC_SUCCESS; } |