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| author | Shelton Leung <sleung@us.ibm.com> | 2017-02-11 08:24:39 -0600 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-02-14 17:41:18 -0500 |
| commit | 441fb19059b39a3d440f6db17278fb9567b80e5f (patch) | |
| tree | 6359befeac93570ad54eaf32734aae025f0e6b39 /src/import/chips | |
| parent | c7588688e17ca4390e790e2939667c4009d04c6a (diff) | |
| download | talos-hostboot-441fb19059b39a3d440f6db17278fb9567b80e5f.tar.gz talos-hostboot-441fb19059b39a3d440f6db17278fb9567b80e5f.zip | |
Fifo mode inits now dictated by attribute
Change-Id: I203b4b1ff42e08a0aec71955e2a8fa51f9a463c9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36330
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Dev-Ready: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36331
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/initfiles/p9.mca.scom.initfile | 10 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C | 9 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile index bbc1e5cd5..8ff837ba8 100644 --- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile @@ -657,6 +657,16 @@ ispy MCP.PORT0.SRQ.PC.MBAREF0Q_CFG_REFR_CHECK_INTERVAL [when=S] { ( def_REFRESH_INTERVAL * def_NUM_RANKS * 6 ) / 5; } +ispy MCP.PORT0.SRQ.MBA_WRQ0Q_CFG_WRQ_FIFO_MODE [when=S] { + spyv; + MCBIST.ATTR_MSS_REORDER_QUEUE_SETTING; +} + +ispy MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RRQ_FIFO_MODE [when=S] { + spyv; + MCBIST.ATTR_MSS_REORDER_QUEUE_SETTING; +} + #################################################### diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C index 8fbdf73e8..10fdee5f6 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C @@ -142,6 +142,8 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0, FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TRRD_S, TGT2, l_TGT2_ATTR_EFF_DRAM_TRRD_S)); fapi2::ATTR_EFF_DRAM_TRRD_L_Type l_TGT2_ATTR_EFF_DRAM_TRRD_L; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TRRD_L, TGT2, l_TGT2_ATTR_EFF_DRAM_TRRD_L)); + fapi2::ATTR_MSS_REORDER_QUEUE_SETTING_Type l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_REORDER_QUEUE_SETTING, TGT1, l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING)); fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_Type l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, TGT2, l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM)); uint64_t l_def_SLOT0_DENOMINATOR = ((l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == @@ -401,8 +403,15 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0, FAPI_TRY(fapi2::putScom(TGT0, 0x701090cull, l_scom_buffer)); } { + FAPI_TRY(fapi2::getScom( TGT0, 0x701090dull, l_scom_buffer )); + + l_scom_buffer.insert<5, 1, 63, uint64_t>(l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING ); + FAPI_TRY(fapi2::putScom(TGT0, 0x701090dull, l_scom_buffer)); + } + { FAPI_TRY(fapi2::getScom( TGT0, 0x701090eull, l_scom_buffer )); + l_scom_buffer.insert<6, 1, 63, uint64_t>(l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING ); l_scom_buffer.insert<24, 6, 58, uint64_t>(literal_0b011000 ); FAPI_TRY(fapi2::putScom(TGT0, 0x701090eull, l_scom_buffer)); } |
