diff options
| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-10-21 02:07:16 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-12-05 18:36:43 -0500 |
| commit | 39e3956aba9ee7b7edf53aadcdec8f506429369b (patch) | |
| tree | 7aaa79c29275f78ef1e4319e0af25477cfd7277e /src/import/chips | |
| parent | 8047a6422e3d7a205ea7496c94c986d10de1f094 (diff) | |
| download | talos-hostboot-39e3956aba9ee7b7edf53aadcdec8f506429369b.tar.gz talos-hostboot-39e3956aba9ee7b7edf53aadcdec8f506429369b.zip | |
PM: Image layout change for CME/SGPE Region of P9 HOMER.
- implements compact image layout for CME
- implements compact image layout for SGPE
- enhances ring debug infrastructure
- implements size check for consolidated CME/SGPE SRAM Image.
- Reversal of magic byte used to represent FUSED and NON FUSED core.
- enhances putring to support scan ring overrides.
- added gptr and time rings
- updated in SGPE debug pointer location and boot loader constants.
- Fixed ex instance ring issue (need to skip conversion of scan
region type for ex instance ring)
- memset for CME, SGPE override offset init and
sanity check in ring code.
Change-Id: Ifb6157dd73a24e0158e6a5f39844d897fba6af56
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32544
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32567
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
10 files changed, 952 insertions, 672 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index e856471a4..670028cbe 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -58,6 +58,7 @@ CONST_UINT32_T(QPMR_HEADER_SIZE, 512); HCD_MAGIC_NUMBER(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)); // CPMR_1.0 HCD_MAGIC_NUMBER(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)); // QPMR_1.0 HCD_MAGIC_NUMBER(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)); // CME__1.0 +HCD_MAGIC_NUMBER(SGPE_MAGIC_NUMBER, ULL(0x534750455f312e30 )); // SGPE_1.0 HCD_MAGIC_NUMBER(PGPE_MAGIC_NUMBER , ULL(0x504750455F312E30)); // PGPE_1.0 @@ -86,13 +87,16 @@ HCD_HDR_UINT32( sgpeImgOffset, 0); HCD_HDR_UINT32( sgpeImgLength, 0); HCD_HDR_UINT32( quadCommonRingOffset, 0); HCD_HDR_UINT32( quadCommonRingLength, 0); +HCD_HDR_UINT32( quadCommonOvrdOffset, 0 ); +HCD_HDR_UINT32( quadCommonOvrdLength, 0 ); HCD_HDR_UINT32( quadSpecRingOffset, 0); HCD_HDR_UINT32( quadSpecRingLength, 0); -HCD_HDR_UINT32( quadSpecScomOffset, 0); -HCD_HDR_UINT32( quadSpecScomLength, 0); -HCD_HDR_UINT32( quadCmnRingOccOffset, 0); -HCD_HDR_UINT32( quadSpecRingOccOffset, 0); -HCD_HDR_UINT32( quadCmnScomOccOffset, 0); +HCD_HDR_UINT32( quadScomOffset, 0); +HCD_HDR_UINT32( quadScomLength, 0); +HCD_HDR_UINT32( quad24x7Offset, 0); +HCD_HDR_UINT32( quad24x7Length, 0); +HCD_HDR_UINT32( stopFfdcOffset, 0); +HCD_HDR_UINT32( stopFfdcLength, 0); HCD_HDR_PAD(512); #ifdef __ASSEMBLER__ .endm @@ -176,9 +180,9 @@ HCD_HDR_UINT64(g_sgpe_reserve_flags, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); -HCD_HDR_UINT32(g_sgpe_cmn_scom_offset, 0); -HCD_HDR_UINT32(g_sgpe_cmn_scom_mem_offset, 0); -HCD_HDR_UINT32(g_sgpe_cmn_scom_length, 0); +HCD_HDR_UINT32(g_sgpe_scom_offset, 0); +HCD_HDR_UINT32(g_sgpe_scom_mem_offset, 0); +HCD_HDR_UINT32(g_sgpe_scom_mem_length, 0); HCD_HDR_UINT32(g_sgpe_24x7_offset, 0); HCD_HDR_UINT32(g_sgpe_24x7_length, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); @@ -217,12 +221,12 @@ HCD_HDR_UINT32(g_cme_common_ring_length, 0); HCD_HDR_UINT32(g_cme_pstate_region_offset, 0); HCD_HDR_UINT32(g_cme_pstate_region_length, 0); HCD_HDR_UINT32(g_cme_core_spec_ring_offset, 0); -HCD_HDR_UINT32(g_cme_core_spec_ring_ovrd_offset, 0); HCD_HDR_UINT32(g_cme_max_spec_ring_length, 0); HCD_HDR_UINT32(g_cme_scom_offset, 0); HCD_HDR_UINT32(g_cme_scom_length, 0); HCD_HDR_UINT32(g_cme_mode_flags, 0); HCD_HDR_UINT32(g_cme_reserved1, 0); +HCD_HDR_UINT32(g_cme_reserved2, 0); //Retain next field at 8B boundary HCD_HDR_UINT64(g_cme_cpmr_PhyAddr, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ @@ -301,8 +305,8 @@ enum CORE0_CHIPLET_ID = 0x20, PAD_OPCODE = 0x00000200, //ATTN Opcode PPE_RESERVE_AREA = 0x200, - FUSE_STATE = 0xAA, - UNFUSE_STATE = 0xBB, + FUSED_MODE = 0xBB, + NONFUSED_MODE = 0xAA, PK_DBG_PTR_AREA_SIZE = 64, SCOM_ENTRY_SIZE = 16, // 4B pad, 4B address, 8B data @@ -319,8 +323,7 @@ enum SGPE_DBG_PTR_AREA_SIZE = 64, SGPE_HCODE_SIZE = (45 * ONE_KB) + HALF_KB, // @todo RTC 158543 Reallocate space - SGPE_EXE_SIZE = (SGPE_HCODE_SIZE - ( SGPE_INT_VECT + - SGPE_IMG_HEADER + PK_DBG_PTR_AREA_SIZE )), + SGPE_IMAGE_SIZE = 80 * ONE_KB, SGPE_ALLOCATED_SIZE = SGPE_HCODE_SIZE, // @todo RTC 158543 Reallocate space (collapse??) @@ -369,10 +372,11 @@ enum CME_INT_VECTOR_SIZE = 384, CME_IMG_HEADER_SIZE = 64, CPMR_CME_HCODE_OFFSET = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_HCODE_SIZE = (30 * ONE_KB), //FIXME RTC 159737 Needs review before merge of P-State + CME_REGION_SIZE = (64 * ONE_KB), // CME hcode and data's footprint in HOMER + CME_SRAM_SIZE = (32 * ONE_KB ), //** Scan - CORE_COMMON_RING_SIZE = 1 * ONE_KB, // common ring( 2KB) + common overrides (1KB) + CORE_COMMON_RING_SIZE = 2 * ONE_KB, // common ring( 2KB) + common overrides (1KB) MAX_SIZE_CME_INST_RING = 1 * ONE_KB, CORE_OVERRIDE_RING = 1 * ONE_KB, // common for all cores QUAD_PSTATE_SIZE = HALF_KB, // common for all cores @@ -381,10 +385,6 @@ enum CME_SRAM_HCODE_OFFSET = 0x00, //(???) CME_INST_SPEC_RING_START = 300 * ONE_KB, CME_REGION_START = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - RESERVE_CME_RING_AREA = ( CME_INST_SPEC_RING_START - ( CME_REGION_START + - CME_HCODE_SIZE + - CORE_COMMON_RING_SIZE + - QUAD_PSTATE_SIZE)), CME_BLOCK_READ_LEN = 32, CME_BLK_SIZE_SHIFT = 0x05, @@ -442,6 +442,9 @@ enum ImgBldRetCode_t BUILD_SEC_SIZE_OVERFLOW = 28, BUILD_FAIL_INVALID_SECTN = 29, BUILD_FAIL_RING_EXTRACTN = 30, + CME_SRAM_IMG_SIZE_ERR = 31, + SGPE_SRAM_IMG_SIZE_ERR = 32, + PGPE_SRAM_IMG_SIZE_ERR = 33, }; /** @@ -599,12 +602,7 @@ typedef struct uint8_t qpmrHeader[sizeof(QpmrHeaderLayout_t)]; uint8_t l1BootLoader[SGPE_LVL_1_BOOT_LOAD_SIZE]; uint8_t l2BootLoader[SGPE_LVL_2_BOOT_LOAD_SIZE]; - uint8_t hcodeIntVect[SGPE_INT_VECT]; - uint8_t imgHeader[sizeof(sgpeHeader_t)]; - uint8_t debugPtrs[PK_DBG_PTR_AREA_SIZE]; - uint8_t hcode[SGPE_EXE_SIZE]; - CmnRingLayoutSgpe_t quadCmnRingArea; - InstRingLayoutSgpe_t quadSpecRingArea; + uint8_t sgpeSramImage[SGPE_IMAGE_SIZE]; } SgpeLayout_t; typedef union CPMRSelfRestoreLayout @@ -628,26 +626,10 @@ typedef struct uint8_t coreScom[CORE_SCOM_RES_SIZE]; } SelfRestoreLayout_t; -typedef union CmeHcodeLayout -{ - uint8_t hcode[CME_HCODE_SIZE]; - struct - { - uint8_t cmeIntVector[CME_INT_VECTOR_SIZE]; - cmeHeader_t imgHeader; - uint8_t exe[CME_HCODE_SIZE - CME_INT_VECTOR_SIZE - sizeof(cmeHeader_t)]; - } elements; -} CmeHcodeLayout_t; - - typedef struct { SelfRestoreLayout_t selfRestoreRegion; - CmeHcodeLayout_t cmeBin; - CoreCmnRingLayout_t coreCmnRingArea; - uint8_t quadPstateArea[QUAD_PSTATE_SIZE]; - uint8_t resvRingArea[RESERVE_CME_RING_AREA]; - CoreSpecRingLayout_t coreSpecRingArea[MAX_CME_PER_CHIP]; + uint8_t cmeSramRegion[CME_REGION_SIZE]; } CPMRLayout_t; /** diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H b/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H index 64cf09c74..468bb741f 100755 --- a/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H @@ -88,11 +88,11 @@ namespace stopImageSection typedef struct { uint64_t attnOpcodes; - uint64_t homerMagicNumber; + uint64_t cpmrMagicWord; uint32_t buildDate; uint32_t version; uint8_t reserve1[7]; - uint8_t fuseModeStatus; + uint8_t fusedModeStatus; uint32_t cmeImgOffset; uint32_t cmeImgLength; uint32_t cmeCommonRingOffset; @@ -111,10 +111,10 @@ typedef struct */ enum { - FUSE_BIT0 = 0x08, - FUSE_BIT1 = 0x04, - FUSE_BIT2 = 0x02, - FUSE_BIT3 = 0x01, + FUSED_CORE_BIT0 = 0x08, + FUSED_CORE_BIT1 = 0x04, + FUSED_CORE_BIT2 = 0x02, + FUSED_CORE_BIT3 = 0x01, QUAD_BITS = 0x70 }; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 4645df8f1..48a929d56 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -73,12 +73,25 @@ extern "C" * @param RING_REGION_BASE start location of scan ring region in HOMER. * @param RING_LOC start of scan ring. */ -#define ALGIN_RING_LOC(RING_REGION_BASE, RING_LOC) \ +#define ALIGN_RING_LOC(RING_REGION_BASE, RING_LOC) \ { \ uint8_t tempDiff = \ (uint8_t *) RING_LOC - (uint8_t *) RING_REGION_BASE; \ - if(tempDiff) \ - { RING_LOC = RING_LOC + 8 - (tempDiff % 8) ; \ + tempDiff = tempDiff %8; \ + if( ( tempDiff > 0 ) && ( tempDiff < 8 )) \ + { RING_LOC = RING_LOC + 8 - tempDiff; \ + } \ + } + + /** + * @brief round of ring size to multiple of 32B + */ +#define ROUND_OFF_32B( ROUND_SIZE) \ + { \ + uint32_t tempSize = ROUND_SIZE; \ + if( tempSize ) \ + { \ + ROUND_SIZE = (( ( tempSize + 31 )/32 ) * 32 ); \ } \ } namespace p9_hcodeImageBuild @@ -134,7 +147,7 @@ extern "C" }; /** - * @brief models an section in HOMER. + * @brief models a section in HOMER. */ struct ImgSec { @@ -206,14 +219,14 @@ extern "C" iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR)] = HALF_KB; iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL)] = SGPE_LVL_1_BOOT_LOAD_SIZE; iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL2_BL)] = SGPE_LVL_2_BOOT_LOAD_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE)] = SGPE_HCODE_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE)] = SGPE_IMAGE_SIZE; - iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE)] = CME_HCODE_SIZE; + iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE)] = CME_SRAM_SIZE; //iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPPMR)] = HALF_KB; iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL)] = PGPE_LVL_1_BOOT_LOAD_SIZE ; iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL)] = PGPE_LVL_2_BOOT_LOAD_SIZE ; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE)] = PGPE_HCODE_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE)] = PGPE_MAX_AREA_SIZE; } /** @@ -244,7 +257,7 @@ extern "C" } } - FAPI_DBG(" Sec Size 0x%08x", size); + FAPI_DBG(" Sec Size 0x%08X", size); return size; } @@ -292,7 +305,7 @@ extern "C" { 0x14, 0x15 }, { 0x16, 0x17 }, { 0x18, 0x19 }, - { 0x20, 0x21 } + { 0x1A, 0x1B } }; for( uint32_t eqCnt = 0; eqCnt < MAX_CACHE_CHIPLET; eqCnt++ ) @@ -356,6 +369,51 @@ extern "C" //------------------------------------------------------------------------- + uint32_t validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize ) + { + FAPI_DBG(">validateSramImageSize" ); + uint32_t rc = IMG_BUILD_SUCCESS; + + do + { + ImgSizeBank sizebank; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + + //FIXME size will change once SCOM and 24x7 are handled + o_sramImgSize = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset); + + rc = sizebank.isSizeGood( PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE, o_sramImgSize ); + FAPI_DBG("SGPE SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + + if( rc ) + { + rc = SGPE_SRAM_IMG_SIZE_ERR; + break; + } + + o_sramImgSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset) << CME_BLK_SIZE_SHIFT) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length); + + FAPI_DBG("CME Offset 0x%08X size 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset), o_sramImgSize ); + rc = sizebank.isSizeGood( PLAT_CME, P9_XIP_SECTION_CME_HCODE, o_sramImgSize ); + FAPI_DBG("CME SRAM Image : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + + if( rc ) + { + rc = CME_SRAM_IMG_SIZE_ERR; + break; + } + } + while(0); + + FAPI_DBG("<validateSramImageSize" ); + + return rc; + } + + //------------------------------------------------------------------------- + /** * @brief validates arguments passed for hcode image build * @param refer to p9_hcode_image_build arguments @@ -379,7 +437,7 @@ extern "C" "Bad pointer to HW Image or HOMER Image" ); l_rc = p9_xip_image_size( i_pImageIn, &hwImagSize ); - FAPI_DBG("size is 0x%08x; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08x Sz 0x%08x", + FAPI_DBG("size is 0x%08X; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08X Sz 0x%08X", hwImagSize, l_rc, HARDWARE_IMG_SIZE, hwImagSize ); FAPI_ASSERT( (( IMG_BUILD_SUCCESS == l_rc ) && ( hwImagSize > 0 ) && @@ -449,7 +507,7 @@ extern "C" if( rcTemp ) { - FAPI_ERR("Failed to get section 0x%08x of Plat 0x%08x", i_secId, i_platId ); + FAPI_ERR("Failed to get section 0x%08X of Plat 0x%08X", i_secId, i_platId ); retCode = BUILD_FAIL_INVALID_SECTN; break; } @@ -466,7 +524,7 @@ extern "C" if ( rcTemp ) { FAPI_ERR("??????????Size Exceeds the permissible limit???????" ); - FAPI_ERR("Max Allowed 0x%08x (%08d) Actual Size 0x%08x (%08d)", + FAPI_ERR("Max Allowed 0x%08X (%08d) Actual Size 0x%08X (%08d)", rcTemp, rcTemp, o_ppeSection.iv_size, o_ppeSection.iv_size); retCode = BUILD_SEC_SIZE_OVERFLOW; break; @@ -483,84 +541,63 @@ extern "C" //------------------------------------------------------------------------------ /** - * @brief updates various CPMR fields which are not associated with scan rings. - * @param i_pChipHomer points to start of P9 HOMER. - */ - void updateCpmrHeaderCME( Homerlayout_t* i_pChipHomer ) - { - FAPI_INF("> updateCpmrHeaderCME"); - - cpmrHeader_t* pCpmrHdr = - (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - - cmeHeader_t* pCmeHdr = NULL; - pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeBin.elements.imgHeader; - - - //offset is multiple of 32B for quick setting of MBASE of CME's BCE - pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CPMR_CME_HCODE_OFFSET >> CME_BLK_SIZE_SHIFT)); - // populate the CME binary's size - pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length; - - pCpmrHdr->cmePstateOffset = 0; - pCpmrHdr->cmePstateLength = 0; - pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE((CORE_SCOM_START >> CME_BLK_SIZE_SHIFT)); - pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE((CORE_SCOM_RES_SIZE >> CME_BLK_SIZE_SHIFT)); - - FAPI_INF("< updateCpmrHeaderCME"); - } - -//------------------------------------------------------------------------------ - - /** * @brief updates various CPMR fields which are associated with scan rings. * @param i_pChipHomer points to start of P9 HOMER. */ - void updateCpmrScanRing( Homerlayout_t* i_pChipHomer ) + void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) { cpmrHeader_t* pCpmrHdr = (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - cmeHeader_t* pCmeHdr = NULL; - pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeBin.elements.imgHeader; - //FIXME Populating select fields with MAX possible size to assist booting. Will revisit it later - pCpmrHdr->cmeCommonRingOffset = (uint8_t*) &i_pChipHomer->cpmrRegion.coreCmnRingArea.cmnRingIndex - - (uint8_t*) &i_pChipHomer->cpmrRegion; - pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset); - pCpmrHdr->cmeImgLength = SWIZZLE_4_BYTE( CME_HCODE_SIZE ); + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + + //Updating CPMR Header using info from CME Header + pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CPMR_CME_HCODE_OFFSET >> CME_BLK_SIZE_SHIFT)); + pCpmrHdr->cmePstateOffset = CPMR_CME_HCODE_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); + pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset); + pCpmrHdr->cmePstateLength = 0; + pCpmrHdr->cmeCommonRingOffset = CPMR_CME_HCODE_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset); + pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled pCpmrHdr->cmeCommonRingLength = pCmeHdr->g_cme_common_ring_length; - pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(CME_INST_SPEC_RING_START); - pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length)); - pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_PER_CME); + pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(CME_INST_SPEC_RING_START); + pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled + pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_START); + pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RES_SIZE); + + //Updating CME Image header + pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER); + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); //Multiple of 32B block + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); + pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_PER_CME); FAPI_INF("========================= CME Header Start =================================="); - FAPI_INF(" Magic Num = 0x%16lX", SWIZZLE_8_BYTE(pCmeHdr->g_cme_magic_number)); + FAPI_INF(" Magic Num = 0x%16lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_magic_number)); FAPI_INF(" HC Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset)); FAPI_INF(" HC Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length)); - FAPI_INF(" CR Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); - FAPI_INF(" CR Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); - FAPI_INF(" CR Ovrd Offset = 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset )); - FAPI_INF(" CSR Offset = 0x%08x (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); FAPI_INF(" PS Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); FAPI_INF(" PS Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length)); - FAPI_INF(" CSR Length = 0x%08x (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); - FAPI_INF(" CPMR Phy Add = 0x%016lX", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); + FAPI_INF(" CR Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); + FAPI_INF(" CR Size = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); + FAPI_INF(" CR Ovrd Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset )); + FAPI_INF(" CSR Offset = 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); + FAPI_INF(" CSR Length = 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); + FAPI_INF(" CPMR Phy Add = 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); FAPI_INF(" SCOM Offset = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset)); FAPI_INF(" SCOM Area Len = 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length)); FAPI_INF("========================= CME Header End =================================="); FAPI_INF("==========================CPMR Header==========================================="); - FAPI_INF(" CME HC Offset : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); - FAPI_INF(" CME HC Length : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); - FAPI_INF(" CR Offset : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset)); - FAPI_INF(" CR Length : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength)); - FAPI_INF(" PS Offset : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); - FAPI_INF(" PS Length : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength)); - FAPI_INF(" CSR Offset : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)); - FAPI_INF(" CSR Length : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)); - FAPI_INF(" Core SCOM Offset : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); - FAPI_INF(" Core SCOM Length : 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); + FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); + FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); + FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength)); + FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset)); + FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength)); + FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)); + FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)); + FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); + FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); FAPI_INF("==================================CPMR Ends====================================="); } @@ -571,21 +608,19 @@ extern "C" * @param i_pChipHomer points to start of P9 HOMER. * @param i_fuseState core fuse status */ - void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fuseState ) + void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) { FAPI_INF("> updateCpmrHeaderSR"); cpmrHeader_t* pCpmrHdr = (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - cmeHeader_t* pCmeHdr = NULL; - pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeBin.elements.imgHeader; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; //populate CPMR header - pCpmrHdr->fuseModeStatus = SWIZZLE_4_BYTE(i_fuseState ? FUSE_STATE : UNFUSE_STATE); - - pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fuseState ? 1 : 0); + pCpmrHdr->fuseModeStatus = i_fusedState ? FUSED_MODE : NONFUSED_MODE; + pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); FAPI_INF("CPMR SR"); - FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->fuseModeStatus), + FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fuseModeStatus, SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, @@ -606,18 +641,11 @@ extern "C" uint32_t rc = IMG_BUILD_SUCCESS; QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader); - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.imgHeader; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) ); - pQpmrHdr->sgpeImgLength = SWIZZLE_4_BYTE(SGPE_HCODE_SIZE); - pQpmrHdr->quadSpecRingLength = SWIZZLE_4_BYTE(CACHE_INST_SPECIFIC_SIZE); - pQpmrHdr->quadCommonRingLength = SWIZZLE_4_BYTE(SGPE_COMMON_RING_SIZE); - pQpmrHdr->quadCommonRingOffset = (uint8_t*) - &i_pChipHomer->qpmrRegion.sgpeRegion.quadCmnRingArea.cmnRingIndex.quadCmnRingList - - (uint8_t*) &i_pChipHomer->qpmrRegion.sgpeRegion; - pQpmrHdr->quadCommonRingOffset = SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset); - - //To take care of holes within sections, updating SGPE Image header with MAX section size. + pQpmrHdr->magic_number = SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER); + pSgpeHdr->g_sgpe_magic_number = SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER); pSgpeHdr->g_sgpe_cmn_ring_occ_offset = pQpmrHdr->sgpeImgLength; pSgpeHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset) + SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength); @@ -632,21 +660,23 @@ extern "C" FAPI_INF(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength)); FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset)); FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength)); - FAPI_DBG(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) ); - FAPI_DBG(" Cmn Ring Length : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) ); - FAPI_DBG(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) ); - FAPI_DBG(" Quad Spec Ring Length : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) ); + FAPI_DBG(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) ); + FAPI_DBG(" Cmn Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) ); + FAPI_DBG(" Cmn Ring Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdOffset) ); + FAPI_DBG(" Cmn Ring Ovrd Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdLength) ); + FAPI_DBG(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) ); + FAPI_DBG(" Quad Spec Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) ); FAPI_INF("==============================QPMR Ends=============================="); FAPI_INF("===========================SGPE Image Hdr============================="); - FAPI_INF(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset )); - FAPI_INF(" Override Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset )); - FAPI_INF(" Flags : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags )); - FAPI_INF(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset )); - FAPI_INF(" Quad SCOM SRAM Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_scom_offset)); - FAPI_INF(" Quad SCOM Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_scom_mem_offset)); - FAPI_INF(" Quad SCOM Mem Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_scom_length )); - FAPI_INF(" 24x7 Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset )); - FAPI_INF(" 24x7 Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_scom_length )); + FAPI_INF(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset )); + FAPI_INF(" Override Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset )); + FAPI_INF(" Flags : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags )); + FAPI_INF(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset )); + FAPI_INF(" Quad SCOM SRAM Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset)); + FAPI_INF(" Quad SCOM Mem Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset)); + FAPI_INF(" Quad SCOM Mem Length : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length )); + FAPI_INF(" 24x7 Offset : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset )); + FAPI_INF(" 24x7 Length : 0x%08X", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_length )); FAPI_INF("========================SGPE Image Hdr Ends==========================="); return rc; @@ -677,6 +707,8 @@ extern "C" break; } + // Let us start with a clean slate in quad common ring area. + memset( (uint8_t*)&i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, 0x00, SGPE_IMAGE_SIZE ); rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_SGPE, &ppeSection ); if( rcTemp ) @@ -745,10 +777,7 @@ extern "C" FAPI_INF("SGPE Boot Loader QPMR Offset = 0x%08X, Size = 0x%08X", o_qpmrHdr.bootLoaderOffset, o_qpmrHdr.bootLoaderLength); - // The image in the HW Image has the Interrupt Vectors, SGPE Header and Debug - // Pointer already included. Thus, load the "Hcode Image" starting at the - // sgpeRegion.hcodeIntVect location. - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.hcodeIntVect, + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, pSgpeImg, P9_XIP_SECTION_SGPE_HCODE, PLAT_SGPE, @@ -769,7 +798,7 @@ extern "C" o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE; - o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(SGPE_HCODE_SIZE); + o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(ppeSection.iv_size); o_qpmrHdr.bootLoaderOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset); //let us take care of endianess now. o_qpmrHdr.bootCopierOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootCopierOffset); @@ -778,10 +807,10 @@ extern "C" //FIXME Need to confirm it - o_qpmrHdr.quadSpecScomOffset = SWIZZLE_4_BYTE(CACHE_SCOM_START); + o_qpmrHdr.quadScomOffset = SWIZZLE_4_BYTE(CACHE_SCOM_START); - sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.imgHeader; - pImgHdr->g_sgpe_cmn_ring_occ_offset = SWIZZLE_4_BYTE(SGPE_ALLOCATED_SIZE); + sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; + pImgHdr->g_sgpe_cmn_ring_occ_offset = o_qpmrHdr.sgpeImgLength; FAPI_INF("SGPE Header"); FAPI_INF(" Magic Num = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number)); @@ -810,7 +839,7 @@ extern "C" */ uint32_t buildCoreRestoreImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, - uint8_t i_fuseState ) + uint8_t i_fusedState ) { uint32_t retCode = IMG_BUILD_SUCCESS; @@ -882,7 +911,7 @@ extern "C" wordCnt += 4; } - updateCpmrHeaderSR( i_pChipHomer, i_fuseState ); + updateCpmrHeaderSR( i_pChipHomer, i_fusedState ); } while(0); @@ -923,43 +952,52 @@ extern "C" FAPI_DBG("ppeSection.iv_offset = 0x%08X, ppeSection.iv_size = 0x%08X", ppeSection.iv_offset, ppeSection.iv_size); - if( i_imgType.cmeHcodeBuild ) + if( !i_imgType.cmeHcodeBuild ) { - // The image in the HW Image has the Interrupt Vectors, CME Header and Debug - // Pointers already included. - rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.cmeBin.hcode, pCmeImg, - P9_XIP_SECTION_CME_HCODE, - PLAT_CME, - ppeSection ); + break; + } - if( rcTemp ) - { - FAPI_ERR("Failed to append CME Hcode"); - retCode = BUILD_FAIL_CME_HCODE; - break; - } + memset(i_pChipHomer->cpmrRegion.cmeSramRegion, 0x00, CME_REGION_SIZE); - // Initializing CME Image header - // Names have g_ prefix as these global variables for CME Hcode - // Note: Only the *memory* addresses are updated - cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeBin.elements.imgHeader; - pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(CME_SRAM_HCODE_OFFSET); - pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(CME_HCODE_SIZE); - - //Populating common ring offset here. So, that other scan ring related field can be updated. - pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset) + - SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); - pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); - pImgHdr->g_cme_cpmr_PhyAddr = SWIZZLE_8_BYTE(i_cpmrPhyAdd | CPMR_OFFSET); - pImgHdr->g_cme_scom_offset = 0; - pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_PER_CME); - pImgHdr->g_cme_common_ring_length = 0; - pImgHdr->g_cme_pstate_region_offset = 0; - pImgHdr->g_cme_pstate_region_length = 0; - pImgHdr->g_cme_core_spec_ring_offset = 0; // multiple of 32B blocks - pImgHdr->g_cme_max_spec_ring_length = 0; // multiple of 32B blocks + // The image in the HW Image has the Interrupt Vectors, CME Header and Debug + // Pointers already included. + rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.cmeSramRegion, pCmeImg, + P9_XIP_SECTION_CME_HCODE, + PLAT_CME, + ppeSection ); + if( rcTemp ) + { + FAPI_ERR("Failed to append CME Hcode"); + retCode = BUILD_FAIL_CME_HCODE; + break; } + + // Initializing CME Image header + // Names have g_ prefix as these global variables for CME Hcode + // Note: Only the *memory* addresses are updated + cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; + pImgHdr->g_cme_hcode_length = ppeSection.iv_size; + + //Populating common ring offset here. So, that other scan ring related field can be updated. + pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_OFFSET); + pImgHdr->g_cme_pstate_region_offset = pImgHdr->g_cme_hcode_offset + pImgHdr->g_cme_hcode_length; + pImgHdr->g_cme_pstate_region_length = 0; + pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_pstate_region_offset + pImgHdr->g_cme_pstate_region_length; + pImgHdr->g_cme_common_ring_length = 0; + pImgHdr->g_cme_scom_offset = 0; + pImgHdr->g_cme_scom_length = CORE_SCOM_PER_CME; + pImgHdr->g_cme_core_spec_ring_offset = 0; // multiple of 32B blocks + pImgHdr->g_cme_max_spec_ring_length = 0; // multiple of 32B blocks + + //Let us handle the endianess at the end + pImgHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_pstate_region_offset); + pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); + pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset); + pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); + pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_scom_length); + pImgHdr->g_cme_cpmr_PhyAddr = SWIZZLE_8_BYTE(pImgHdr->g_cme_cpmr_PhyAddr); } while(0); @@ -1090,11 +1128,11 @@ extern "C" } FAPI_DBG("================== Input Buffer Specs ===================="); - FAPI_DBG("Ring section (buf,size)=(0x%016llx,0x%08x)", + FAPI_DBG("Ring section (buf,size)=(0x%016llX,0x%08X)", (uintptr_t)(i_ringData.iv_pRingBuffer), i_ringData.iv_ringBufSize); - FAPI_DBG("Work buf1 (buf,size)=(0x%016llx,0x%08x)", + FAPI_DBG("Work buf1 (buf,size)=(0x%016llX,0x%08X)", (uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1); - FAPI_DBG("Work buf2 (buf,size)=(0x%016llx,0x%08x)", + FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", (uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2); FAPI_DBG("================== Buffer Specs Ends ===================="); @@ -1132,114 +1170,17 @@ extern "C" //------------------------------------------------------------------------------ - uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - ImageType_t i_imgType ) - { - FAPI_INF("> layoutCmeScanOverride" ); - uint32_t rc = IMG_BUILD_SUCCESS; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeBin.elements.imgHeader; - RingBucket cmeOvrdRings( PLAT_CME, - (uint8_t*)&i_pHomer->cpmrRegion, - i_debugMode ); - - do - { - if( !i_imgType.cmeCommonRingBuild ) - { - break; - } - - uint32_t tempRingLength = - SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset) - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); - - //Start override ring from the actual end of base common rings. Remeber overrides reside within area - //earmarked for common rings - uint8_t* pOverrideStart = - &i_pHomer->cpmrRegion.coreCmnRingArea.cmnScanRings[tempRingLength]; - uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; - - //get core common rings - uint8_t* pOverrideRingPayload = pOverrideStart + CORE_COMMON_RING_INDEX_SIZE; - uint32_t tempBufSize = 0; - bool overrideNotFound = true; - - for( uint8_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; - ringIndex++ ) - { - tempBufSize = i_ringData.iv_sizeWorkBuf2; - - FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08x", ringIndex); - rc = tor_get_single_ring( i_pOverride, - P9_XIP_MAGIC_SEEPROM, - i_chipState.getChipLevel(), - cmeOvrdRings.getCommonRingId( ringIndex ), - P9_TOR::SBE, - OVERRIDE, - CORE0_CHIPLET_ID, - &i_ringData.iv_pWorkBuf2, - tempBufSize, - 2 ); - - if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) - - { - tempBufSize = 0; - continue; - } - - overrideNotFound = false; - ALIGN_DWORD(tempRingLength, tempBufSize) - ALGIN_RING_LOC( pOverrideStart, pOverrideRingPayload ); - - memcpy( pOverrideRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOverrideRingPayload - pOverrideStart) + RING_START_TO_RS4_OFFSET); - - cmeOvrdRings.setRingOffset(pOverrideRingPayload, cmeOvrdRings.getCommonRingId( ringIndex )); - cmeOvrdRings.setRingSize( cmeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); - - pOverrideRingPayload = pOverrideRingPayload + tempBufSize; - } - - if( overrideNotFound ) - { - FAPI_INF("Overrides not found for CME"); - rc = BUILD_FAIL_OVERRIDE; // Not considered an error - break; - } - - tempRingLength = (pOverrideRingPayload - pOverrideStart ); - - FAPI_DBG( "Override Ring Length 0x%08x", tempRingLength ); - - } - while(0); - - cmeOvrdRings.dumpOverrideRings(); - - FAPI_INF("< layoutCmeScanOverride" ); - return rc; - } - - //------------------------------------------------------------------------------ - uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer, void* i_pOverride, const P9FuncModel& i_chipState, RingBufData& i_ringData, RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, QpmrHeaderLayout_t& i_qpmrHdr, ImageType_t i_imgType ) { FAPI_INF("> layoutSgpeScanOverride "); uint32_t rc = IMG_BUILD_SUCCESS; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.imgHeader; + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; RingBucket sgpeOvrdRings( PLAT_SGPE, (uint8_t*)&i_pHomer->qpmrRegion, i_debugMode ); @@ -1251,12 +1192,17 @@ extern "C" break; } - uint32_t commonRingLength = SWIZZLE_4_BYTE(i_qpmrHdr.quadCommonRingLength); + if( !i_pOverride ) + { + break; + } + + uint32_t commonRingLength = i_qpmrHdr.quadCommonRingLength; //Start override ring from the actual end of base common rings. Remeber overrides reside within area //earmarked for common rings uint8_t* pOverrideStart = - &i_pHomer->qpmrRegion.sgpeRegion.quadCmnRingArea.cmnScanRings[commonRingLength]; + &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[commonRingLength + SWIZZLE_4_BYTE(i_qpmrHdr.sgpeImgLength)]; uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; //get core common rings @@ -1270,7 +1216,7 @@ extern "C" { tempBufSize = i_ringData.iv_sizeWorkBuf1; - FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08x", ringIndex); + FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); rc = tor_get_single_ring( i_pOverride, P9_XIP_MAGIC_SEEPROM, i_chipState.getChipLevel(), @@ -1280,7 +1226,7 @@ extern "C" CACH0_CHIPLET_ID, &i_ringData.iv_pWorkBuf2, tempBufSize, - 2 ); + 1 ); if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || ( 0 != rc ) ) @@ -1291,13 +1237,14 @@ extern "C" overrideNotFound = false; ALIGN_DWORD(tempRingLength, tempBufSize) - ALGIN_RING_LOC( pOverrideStart, pOvrdRingPayload ); + ALIGN_RING_LOC( pOverrideStart, pOvrdRingPayload ); memcpy( pOvrdRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOvrdRingPayload - pOverrideStart) + RING_START_TO_RS4_OFFSET ); sgpeOvrdRings.setRingOffset(pOvrdRingPayload, sgpeOvrdRings.getCommonRingId( ringIndex )); sgpeOvrdRings.setRingSize( sgpeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); + sgpeOvrdRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, sgpeOvrdRings.getCommonRingId( ringIndex ) ); pOvrdRingPayload = pOvrdRingPayload + tempBufSize; } @@ -1312,7 +1259,9 @@ extern "C" tempRingLength = (pOvrdRingPayload - pOverrideStart ); pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) + commonRingLength; - i_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(commonRingLength + tempRingLength); + i_qpmrHdr.quadCommonRingLength = commonRingLength + tempRingLength; + i_qpmrHdr.quadCommonOvrdLength = tempRingLength; + i_qpmrHdr.quadCommonOvrdOffset = i_qpmrHdr.quadCommonRingOffset + commonRingLength; pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset); } @@ -1322,7 +1271,7 @@ extern "C" FAPI_DBG("====================SGPE Override Rings================" ); FAPI_DBG("====================SGPE Header ========================"); - FAPI_DBG("Override Ring Offset 0x%08x", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); + FAPI_DBG("Override Ring Offset 0x%08X", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); FAPI_INF("< layoutSgpeScanOverride") return rc; @@ -1331,101 +1280,120 @@ extern "C" //------------------------------------------------------------------------------ /** - * @brief creates a lean scan ring layout for core rings in HOMER. + * @brief creates a lean scan ring layout for core specific rings in HOMER. * @param i_pHOMER points to HOMER image. - * @param i_ringData processor target - * @param i_riskLevel IPL type + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData scan ring related data + * @param i_debugMode debug type set for scan rings + * @param i_ringVariant scan ring flavor + * @param i_imgType image type to be built + * @param io_cmeRings instance of RingBucket + * @param io_cmnRingSize input: CME region length populated. output: CME region length after copying cmn ring. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. */ - uint32_t layoutRingsForCME( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - ImageType_t i_imgType, - bool i_ovrdPresent ) + uint32_t layoutCmnRingsForCme( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + ImageType_t i_imgType, + RingBucket& io_cmeRings, + uint32_t& io_cmnRingSize ) { - FAPI_DBG( "> layoutRingsForCME"); + FAPI_DBG( "> layoutCmnRingsForCme"); uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; - uint32_t ringLength = 0; - RingVariant_t l_ringVariant = BASE; - uint8_t* pRingPayload = i_pHomer->cpmrRegion.coreCmnRingArea.cmnRingIndex.cmnScanRingPayload; - uint16_t* pScanRingIndex = (uint16_t*)&i_pHomer->cpmrRegion.coreCmnRingArea.cmnRingIndex.cmnRings; - uint8_t* pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.coreCmnRingArea; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeBin.elements.imgHeader; - RingBucket cmeRings( PLAT_CME, - (uint8_t*)&i_pHomer->cpmrRegion, - i_debugMode ); do { + + uint32_t tempSize = 0; + uint32_t ringSize = 0; + uint8_t* pRingStart = &i_pHomer->cpmrRegion.cmeSramRegion[io_cmnRingSize]; + uint16_t* pScanRingIndex = (uint16_t*) pRingStart; + uint8_t* pRingPayload = pRingStart + CORE_COMMON_RING_INDEX_SIZE; + if( !i_imgType.cmeCommonRingBuild ) { break; } - // get all the rings pertaining to CME in a work buffer first. - if( i_riskLevel ) - { - l_ringVariant = RL; - } - - // Let us start with a clean slate in core common ring area. - memset( (uint8_t*)&i_pHomer->cpmrRegion.coreCmnRingArea, 0x00, CORE_COMMON_RING_SIZE ); - for( uint32_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; ringIndex++ ) { - tempBufSize = i_ringData.iv_sizeWorkBuf1; + ringSize = i_ringData.iv_sizeWorkBuf1; rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_CME, i_chipState.getChipLevel(), - cmeRings.getCommonRingId( ringIndex ), + io_cmeRings.getCommonRingId( ringIndex ), P9_TOR::CME, - l_ringVariant, + i_ringVariant, CORE0_CHIPLET_ID , &i_ringData.iv_pWorkBuf1, - tempBufSize, - 2 ); + ringSize, + 1 ); - if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || + if( ( i_ringData.iv_sizeWorkBuf1 == ringSize ) || ( 0 == ringSize ) || ( 0 != rc ) ) { FAPI_INF( "Did not find core common ring Id %d ", ringIndex ); rc = 0; - tempBufSize = 0; + ringSize = 0; continue; } - ALIGN_DWORD(ringLength, tempBufSize) - ALGIN_RING_LOC( pRingStart, pRingPayload ); + ALIGN_DWORD(tempSize, ringSize) + ALIGN_RING_LOC( pRingStart, pRingPayload ); - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - (uint8_t*) pScanRingIndex) + + memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, ringSize ); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart) + RING_START_TO_RS4_OFFSET ); - cmeRings.setRingOffset(pRingPayload, cmeRings.getCommonRingId( ringIndex )); - cmeRings.setRingSize( cmeRings.getCommonRingId( ringIndex ), tempBufSize ); + io_cmeRings.setRingOffset( pRingPayload, io_cmeRings.getCommonRingId( ringIndex )); + io_cmeRings.setRingSize( io_cmeRings.getCommonRingId( ringIndex ), ringSize ); + io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, ringSize, io_cmeRings.getCommonRingId( ringIndex ) ); - pRingPayload = pRingPayload + tempBufSize; - } - - ringLength = (pRingPayload - pRingStart); - - if( i_ovrdPresent ) - { - pCmeHdr->g_cme_common_ring_length = ringLength; //Save ring length in img header - } - else - { - pCmeHdr->g_cme_common_ring_length = CORE_COMMON_RING_SIZE; + pRingPayload = pRingPayload + ringSize; } + io_cmnRingSize += (pRingPayload - pRingStart); + ALIGN_DWORD(tempSize, io_cmnRingSize) } while(0); + FAPI_DBG( "< layoutCmnRingsForCme"); + + return rc; + } + + //------------------------------------------------------------------------------ + /** + * @brief creates a lean scan ring layout for core specific rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData scan ring related data + * @param i_debugMode debug type set for scan rings + * @param i_ringVariant scan ring flavor + * @param i_imgType image type to be built + * @param io_cmeRings instance of RingBucket + * @param io_ringLength input: CME region length populated. Output: Max possible size of instance spec ring + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ + + uint32_t layoutInstRingsForCme( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + ImageType_t i_imgType, + RingBucket& io_cmeRings, + uint32_t& io_ringLength ) + { + FAPI_DBG( "> layoutInstRingsForCme"); + uint32_t rc = IMG_BUILD_SUCCESS; // Let us find out ring-pair which is biggest in list of 12 ring pairs uint32_t maxCoreSpecRingLength = 0; + uint32_t ringLength = 0; + uint32_t tempSize = 0; do { @@ -1452,50 +1420,52 @@ extern "C" continue; } - tempBufSize = i_ringData.iv_sizeWorkBuf1; + tempSize = i_ringData.iv_sizeWorkBuf1; rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_CME, i_chipState.getChipLevel(), - cmeRings.getInstRingId(0), + io_cmeRings.getInstRingId(0), P9_TOR::CME, - l_ringVariant, + i_ringVariant, CORE0_CHIPLET_ID + ((2 * exId) + coreId), &i_ringData.iv_pWorkBuf1, - tempBufSize, 2 ); + tempSize, + 1 ); - if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || + if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || ( 0 != rc ) ) { FAPI_DBG( "could not determine size of ring id %d of core %d", - cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); + io_cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); continue; } - ringLength += tempBufSize; + ringLength += tempSize; } - ALIGN_DWORD(tempBufSize, ringLength) - + ALIGN_DWORD(tempSize, ringLength) maxCoreSpecRingLength = ringLength > maxCoreSpecRingLength ? ringLength : maxCoreSpecRingLength; } maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); - FAPI_DBG("Max Instance Spec Ring 0x%08x", maxCoreSpecRingLength); + ROUND_OFF_32B(maxCoreSpecRingLength); + + FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); // Let us copy the rings now. - // Let us start with a clean slate in core specific ring area. - memset((uint8_t*) &i_pHomer->cpmrRegion.coreSpecRingArea[0], 0x00, (MAX_SIZE_CME_INST_RING * MAX_CME_PER_CHIP) ); + uint8_t* pRingStart = NULL; + uint8_t* pRingPayload = NULL; + uint16_t* pScanRingIndex = NULL; for( uint32_t exId = 0; exId < MAX_CME_PER_CHIP; exId++ ) { - pRingPayload = i_pHomer->cpmrRegion.coreSpecRingArea[exId].instRingIndex.instanceRingPayLoad; - pScanRingIndex = (uint16_t*)&i_pHomer->cpmrRegion.coreSpecRingArea[exId].instRingIndex.coreSpecRings; - pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.coreSpecRingArea[exId]; + pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; + pRingPayload = &i_pHomer->cpmrRegion.cmeSramRegion[ io_ringLength + ( exId * maxCoreSpecRingLength ) ]; + pScanRingIndex = (uint16_t*)pRingStart; if( !i_chipState.isExFunctional( exId ) ) { FAPI_DBG("skipping copy of core specific rings of ex %d", exId); - pRingPayload = pRingStart + ( exId * maxCoreSpecRingLength ); continue; } @@ -1507,75 +1477,255 @@ extern "C" continue; } - tempBufSize = i_ringData.iv_sizeWorkBuf1; + tempSize = i_ringData.iv_sizeWorkBuf1; rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_CME, i_chipState.getChipLevel(), - cmeRings.getInstRingId(0), + io_cmeRings.getInstRingId(0), P9_TOR::CME, - l_ringVariant, + i_ringVariant, CORE0_CHIPLET_ID + ((2 * exId) + coreId), &i_ringData.iv_pWorkBuf1, - tempBufSize ); + tempSize, + 1 ); - if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || + if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || ( 0 != rc ) ) { FAPI_INF("Instance ring Id %d not found for EX %d core %d", - cmeRings.getInstRingId(0), exId, coreId ); + io_cmeRings.getInstRingId(0), exId, coreId ); rc = 0; - tempBufSize = 0; + tempSize = 0; continue; } - ALGIN_RING_LOC( pRingStart, pRingPayload ); - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); - cmeRings.setRingOffset( pRingPayload, - cmeRings.getInstRingId(0), - ( MAX_CORES_PER_EX * exId ) + coreId ); + ALIGN_RING_LOC( pRingStart, pRingPayload ); + memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempSize); + io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, tempSize, io_cmeRings.getInstRingId(0) ); + io_cmeRings.setRingOffset( pRingPayload, + io_cmeRings.getInstRingId(0), + ( MAX_CORES_PER_EX * exId ) + coreId ); *(pScanRingIndex + coreId) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + RING_START_TO_RS4_OFFSET ); - pRingPayload = pRingPayload + tempBufSize; - cmeRings.setRingSize( cmeRings.getInstRingId(0), tempBufSize, ((MAX_CORES_PER_EX * exId) + coreId) ); + pRingPayload = pRingPayload + tempSize; + io_cmeRings.setRingSize( io_cmeRings.getInstRingId(0), tempSize, ((MAX_CORES_PER_EX * exId) + coreId) ); } } - if( i_ovrdPresent ) + io_ringLength = maxCoreSpecRingLength; + } + while(0); + + FAPI_DBG( "< layoutInstRingsForCme"); + + return rc; + } + + //------------------------------------------------------------------------------ + + uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + ImageType_t i_imgType, + uint32_t& io_ovrdRingLength ) + { + FAPI_INF("> layoutCmeScanOverride" ); + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t tempRingLength = io_ovrdRingLength; + uint32_t tempBufSize = 0; + + RingBucket cmeOvrdRings( PLAT_CME, + (uint8_t*)&i_pHomer->cpmrRegion, + i_debugMode ); + + do + { + if( !i_imgType.cmeCommonRingBuild ) + { + break; + } + + //Start override ring from the actual end of base common rings. Remember overrides reside within + //common rings region + uint8_t* pOverrideStart = &i_pHomer->cpmrRegion.cmeSramRegion[tempRingLength]; + uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; + + //get core common rings + uint8_t* pOverrideRingPayload = pOverrideStart + CORE_COMMON_RING_INDEX_SIZE; + bool overrideNotFound = true; + + for( uint8_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; + ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf2; + + FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); + rc = tor_get_single_ring( i_pOverride, + P9_XIP_MAGIC_SEEPROM, + i_chipState.getChipLevel(), + cmeOvrdRings.getCommonRingId( ringIndex ), + P9_TOR::SBE, + OVERRIDE, + CORE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf2, + tempBufSize, + 1 ); + + if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) + + { + tempBufSize = 0; + continue; + } + + overrideNotFound = false; + ALIGN_DWORD(tempRingLength, tempBufSize) + ALIGN_RING_LOC( pOverrideStart, pOverrideRingPayload ); + + memcpy( pOverrideRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOverrideRingPayload - pOverrideStart) + RING_START_TO_RS4_OFFSET); + + cmeOvrdRings.setRingOffset(pOverrideRingPayload, cmeOvrdRings.getCommonRingId( ringIndex )); + cmeOvrdRings.setRingSize( cmeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); + cmeOvrdRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, cmeOvrdRings.getCommonRingId( ringIndex ) ); + + pOverrideRingPayload = pOverrideRingPayload + tempBufSize; + } + + if( overrideNotFound ) { - pCmeHdr->g_cme_cmn_ring_ovrd_offset = - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + pCmeHdr->g_cme_common_ring_length; + FAPI_INF("Overrides not found for CME"); + rc = BUILD_FAIL_OVERRIDE; // Not considered an error + break; } - pCmeHdr->g_cme_common_ring_length = CORE_COMMON_RING_SIZE; - pCmeHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + - pCmeHdr->g_cme_common_ring_length; - pCmeHdr->g_cme_core_spec_ring_offset = pCmeHdr->g_cme_pstate_region_offset + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length); - pCmeHdr->g_cme_core_spec_ring_offset = (pCmeHdr->g_cme_core_spec_ring_offset + CME_BLOCK_READ_LEN - 1 ) >> - CME_BLK_SIZE_SHIFT; - pCmeHdr->g_cme_max_spec_ring_length = ( MAX_SIZE_CME_INST_RING + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT; + io_ovrdRingLength += (pOverrideRingPayload - pOverrideStart ); + ALIGN_DWORD(tempRingLength, io_ovrdRingLength) + + FAPI_DBG( "Override Ring Length 0x%08X", io_ovrdRingLength ); + } + while(0); + + cmeOvrdRings.dumpOverrideRings(); + + FAPI_INF("< layoutCmeScanOverride" ); + return rc; + } + + //------------------------------------------------------------------------------ + + /** + * @brief creates a lean scan ring layout for core rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData processor target + * @param i_debugMode debug mode type for scan rings + * @param i_riskLevel IPL type + * @param i_imgType image type to be built + * @param i_pOverride points to override binary. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ + uint32_t layoutRingsForCME( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + uint32_t i_riskLevel, + ImageType_t i_imgType, + void* i_pOverride ) + { + FAPI_DBG( "> layoutRingsForCME"); + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t ringLength = 0; + uint32_t tempLength = 0; + RingVariant_t l_ringVariant = BASE; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + RingBucket cmeRings( PLAT_CME, + (uint8_t*)&i_pHomer->cpmrRegion, + i_debugMode ); + + do + { + if( !i_imgType.cmeCommonRingBuild ) + { + break; + } + + // get all the rings pertaining to CME in a work buffer first. + if( i_riskLevel ) + { + l_ringVariant = RL; + } + + ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset) + SWIZZLE_4_BYTE( + pCmeHdr->g_cme_pstate_region_length); + tempLength = ringLength; + + layoutCmnRingsForCme( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + i_imgType, + cmeRings, + ringLength ); + + if( i_pOverride ) + { + uint32_t tempOffset = 0; + ALIGN_DWORD( tempOffset, ringLength ); + pCmeHdr->g_cme_cmn_ring_ovrd_offset = ringLength; + + layoutCmeScanOverride( i_pHomer, + i_pOverride, + i_chipState, + i_ringData, + i_debugMode, + i_imgType, + ringLength ); + } + + pCmeHdr->g_cme_common_ring_length = ringLength - tempLength; + pCmeHdr->g_cme_core_spec_ring_offset = + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + pCmeHdr->g_cme_common_ring_length; + pCmeHdr->g_cme_core_spec_ring_offset = + ( ( pCmeHdr->g_cme_core_spec_ring_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT ); + ringLength = (pCmeHdr->g_cme_core_spec_ring_offset << CME_BLK_SIZE_SHIFT ); + + layoutInstRingsForCme( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + i_imgType, + cmeRings, + ringLength ); + + pCmeHdr->g_cme_max_spec_ring_length = ( ringLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT; + //Let us handle endianess now - pCmeHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); + pCmeHdr->g_cme_common_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); pCmeHdr->g_cme_core_spec_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset); pCmeHdr->g_cme_max_spec_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); - pCmeHdr->g_cme_common_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); pCmeHdr->g_cme_cmn_ring_ovrd_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset); } while(0); cmeRings.dumpRings(); FAPI_DBG("CME Header Ring Details "); - FAPI_DBG( "PS Offset %d (0x%08x)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset), + FAPI_DBG( "PS Offset %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset), SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); - FAPI_DBG("PS Lengtrh %d (0x%08x)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length), + FAPI_DBG("PS Lengtrh %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length), SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) ); - FAPI_DBG("Common Ring Offset %d (0x%08x) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset), + FAPI_DBG("Common Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset), SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); - FAPI_DBG("Common Ring Length %d (0x%08x) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length), + FAPI_DBG("Common Ring Length %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length), SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); - FAPI_DBG("Instance Ring Offset / 32 %d (0x%08x) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset), + FAPI_DBG("Instance Ring Offset / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset), SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); - FAPI_DBG("Instance Ring Length / 32 %d (0x%08x) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length), + FAPI_DBG("Instance Ring Length / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length), SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length)); @@ -1584,33 +1734,39 @@ extern "C" return rc; } + //------------------------------------------------------------------------------ /** - * @brief creates a lean scan ring layout for cache rings in HOMER. + * @brief creates a scan ring layout for quad common rings in HOMER. * @param i_pHOMER points to HOMER image. - * @param i_ringData processor target - * @param i_riskLevel IPL type - * @return IMG_BUILD_SUCCESS if success , error code otherwise. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_ringVariant variant of the scan ring to be copied. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param io_sgpeRings stores position and length of all quad common rings. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. */ - uint32_t layoutRingsForSGPE( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - QpmrHeaderLayout_t& i_qpmrHdr, - ImageType_t i_imgType ) + uint32_t layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType, + RingBucket& io_sgpeRings ) { - FAPI_DBG( "> layoutRingsForSGPE"); uint32_t rc = IMG_BUILD_SUCCESS; - RingVariant_t l_ringVariant = BASE; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.imgHeader; - uint8_t* pRingPayload = i_pHomer->qpmrRegion.sgpeRegion.quadCmnRingArea.cmnRingIndex.cmnRingPayLoad; - uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.quadCmnRingArea.cmnRingIndex.quadCmnRingList; - uint8_t* pRingStart = (uint8_t*)&i_pHomer->qpmrRegion.sgpeRegion.quadCmnRingArea; - uint32_t ringIndex = 0; - uint32_t tempLength = 0; - uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; + uint32_t sgpeHcodeSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); + uint8_t* pCmnRingPayload = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize + + QUAD_COMMON_RING_INDEX_SIZE];; + uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; + uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; + uint32_t ringIndex = 0; + uint32_t tempLength = 0; + uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; RingBucket sgpeRings( PLAT_SGPE, (uint8_t*)&i_pHomer->qpmrRegion, @@ -1623,17 +1779,6 @@ extern "C" break; } - // get all the rings pertaining to CME in a work buffer first. - if( i_riskLevel ) - { - l_ringVariant = RL; - } - - // Let us start with a clean slate in quad common ring area. - memset( (uint8_t*)&i_pHomer->qpmrRegion.sgpeRegion.quadCmnRingArea, 0x00, SGPE_COMMON_RING_SIZE ); - - tempLength = (tempBufSize % RING_ALIGN_BOUNDARY); - //get core common rings for( ; ringIndex < EQ::g_eqData.iv_num_common_rings; ringIndex++ ) { @@ -1642,40 +1787,73 @@ extern "C" rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_SGPE, i_chipState.getChipLevel(), - sgpeRings.getCommonRingId( ringIndex ), + io_sgpeRings.getCommonRingId( ringIndex ), P9_TOR::SGPE, - l_ringVariant, + i_ringVariant, CACH0_CHIPLET_ID, &i_ringData.iv_pWorkBuf1, - tempBufSize ); + tempBufSize, + 1 ); if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || ( 0 != rc ) ) { FAPI_INF( "did not find quad common ring %d", ringIndex ); - rc = 0; + rc = IMG_BUILD_SUCCESS; tempBufSize = 0; continue; } ALIGN_DWORD(tempLength, tempBufSize) - ALGIN_RING_LOC( pRingStart, pRingPayload ); + ALIGN_RING_LOC( pRingStart, pCmnRingPayload ); - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); - sgpeRings.setRingOffset( pRingPayload, sgpeRings.getCommonRingId( ringIndex ) ); - *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + RING_START_TO_RS4_OFFSET ); - sgpeRings.setRingSize( sgpeRings.getCommonRingId( ringIndex ), tempBufSize ); - pRingPayload = pRingPayload + tempBufSize; + memcpy( pCmnRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); + io_sgpeRings.setRingOffset( pCmnRingPayload, io_sgpeRings.getCommonRingId( ringIndex ) ); + *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pCmnRingPayload - pRingStart ) + RING_START_TO_RS4_OFFSET ); + io_sgpeRings.setRingSize( io_sgpeRings.getCommonRingId( ringIndex ), tempBufSize ); + io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getCommonRingId( ringIndex ) ); + pCmnRingPayload = pCmnRingPayload + tempBufSize; }//for common rings - tempLength = pRingPayload - pRingStart; - i_qpmrHdr.quadCommonRingLength = tempLength; - FAPI_DBG("Quad Cmn Ring Length 0x%08x", i_qpmrHdr.quadCommonRingLength ); + tempLength = pCmnRingPayload - pRingStart; + io_qpmrHdr.quadCommonRingLength = tempLength; + io_qpmrHdr.quadCommonRingOffset = i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage - + (uint8_t*)&i_pHomer->qpmrRegion; + io_qpmrHdr.quadCommonRingOffset += sgpeHcodeSize; + FAPI_DBG("Quad Cmn Ring Length 0x%08X", io_qpmrHdr.quadCommonRingLength ); } while(0); //building common rings + return rc; + } + + //------------------------------------------------------------------------------ + + /** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_ringVariant variant of the scan ring to be copied. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param io_sgpeRings stores position and length of all quad common rings. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ + uint32_t layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType, + RingBucket& io_sgpeRings ) + { + uint32_t rc = IMG_BUILD_SUCCESS; + do { if( !i_imgType.sgpeCacheSpecificRingBuild ) @@ -1683,12 +1861,11 @@ extern "C" break; } - pRingPayload = i_pHomer->qpmrRegion.sgpeRegion.quadSpecRingArea.instRingIndex.quadSpecRingPayLoad; - pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.quadSpecRingArea.instRingIndex.quadSpecRings[0]; - pRingStart = (uint8_t*)&i_pHomer->qpmrRegion.sgpeRegion.quadSpecRingArea.instRingIndex; - - // Let us start with a clean slate in quad spec ring area. - memset( (uint8_t*)&i_pHomer->qpmrRegion.sgpeRegion.quadSpecRingArea, 0x00, MAX_QUAD_SPEC_RING_SIZE ); + uint32_t quadSpecRingStart = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength; + uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart ]; + uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[quadSpecRingStart]; + uint8_t* instRingPayLoad = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart + + QUAD_SPEC_RING_INDEX_LEN ]; for( uint32_t cacheInst = 0; cacheInst < MAX_CACHE_CHIPLET; cacheInst++ ) { @@ -1702,8 +1879,10 @@ extern "C" ExIdMap ExChipletRingMap; uint32_t chipletId = 0; + uint32_t tempBufSize = 0; + uint32_t tempLength = 0; - for( ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; + for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; ringIndex++ ) { tempBufSize = i_ringData.iv_sizeWorkBuf1; @@ -1712,12 +1891,13 @@ extern "C" rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_SGPE, i_chipState.getChipLevel(), - sgpeRings.getInstRingId( ringIndex ), + io_sgpeRings.getInstRingId( ringIndex ), P9_TOR::SGPE, - l_ringVariant, + i_ringVariant, chipletId, &i_ringData.iv_pWorkBuf1, - tempBufSize ); + tempBufSize, + 1 ); if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || ( 0 != rc ) ) @@ -1729,44 +1909,132 @@ extern "C" } ALIGN_DWORD(tempLength, tempBufSize) - ALGIN_RING_LOC( pRingStart, pRingPayload ); + ALIGN_RING_LOC( pRingStart, instRingPayLoad ); - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); - sgpeRings.setRingOffset( pRingPayload, sgpeRings.getInstRingId( ringIndex ), chipletId ); - *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + RING_START_TO_RS4_OFFSET ); - sgpeRings.setRingSize( sgpeRings.getInstRingId( ringIndex ), tempBufSize, chipletId ); - pRingPayload = pRingPayload + tempBufSize; + memcpy( instRingPayLoad, i_ringData.iv_pWorkBuf1, tempBufSize); + io_sgpeRings.setRingOffset( instRingPayLoad, io_sgpeRings.getInstRingId( ringIndex ), chipletId ); + *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((instRingPayLoad - pRingStart ) + RING_START_TO_RS4_OFFSET ); + io_sgpeRings.setRingSize( io_sgpeRings.getInstRingId( ringIndex ), tempBufSize, chipletId ); + instRingPayLoad = instRingPayLoad + tempBufSize; + io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getInstRingId( ringIndex ) ); }//for quad spec rings pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index } - i_qpmrHdr.quadSpecRingOffset = (uint8_t*)(&i_pHomer->qpmrRegion.sgpeRegion.quadSpecRingArea ) - - (uint8_t*)(&i_pHomer->qpmrRegion); - i_qpmrHdr.quadSpecRingLength = (pRingPayload - pRingStart); + io_qpmrHdr.quadSpecRingOffset = io_qpmrHdr.quadCommonRingOffset + io_qpmrHdr.quadCommonRingLength; + io_qpmrHdr.quadSpecRingLength = (instRingPayLoad - pRingStart); + FAPI_DBG("Instance Ring Length 0x%08X", io_qpmrHdr.quadSpecRingLength); + } + while(0); + + return rc; + } + + //------------------------------------------------------------------------------ + + /** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_riskLevel true if system IPL is in risk level mode else false. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ + uint32_t layoutRingsForSGPE( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + uint32_t i_riskLevel, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType ) + { + FAPI_DBG( "> layoutRingsForSGPE"); + uint32_t rc = IMG_BUILD_SUCCESS; + RingVariant_t l_ringVariant = BASE; + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECT]; + RingBucket sgpeRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); + + do + { + + // get all the rings pertaining to CME in a work buffer first. + if( i_riskLevel ) + { + l_ringVariant = RL; + } + + //Manage the Quad Common rings in HOMER + layoutCmnRingsForSgpe( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + io_qpmrHdr, + i_imgType, + sgpeRings ); + + //Manage the Quad Override rings in HOMER + layoutSgpeScanOverride( i_pHomer, + i_pOverride, + i_chipState, + i_ringData, + i_debugMode, + io_qpmrHdr, + i_imgType ); + + + //Manage the Quad specific rings in HOMER + layoutInstRingsForSgpe( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + io_qpmrHdr, + i_imgType, + sgpeRings ); pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) + - i_qpmrHdr.quadCommonRingLength; + io_qpmrHdr.quadCommonRingLength; + pSgpeImgHdr->g_sgpe_scom_offset = + pSgpeImgHdr->g_sgpe_spec_ring_occ_offset + io_qpmrHdr.quadSpecRingLength; + + FAPI_DBG("SGPE Header Ring Details "); + FAPI_DBG("Common Ring Offset %d (0x%08X) ", + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset), + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset)); + FAPI_DBG("Instance Ring Offset %d (0x%08X) ", + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset), + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset)); } while(0); //building instance rings //Let us handle endianes at last - i_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(i_qpmrHdr.quadCommonRingLength); - i_qpmrHdr.quadSpecRingOffset = SWIZZLE_4_BYTE(i_qpmrHdr.quadSpecRingOffset); - i_qpmrHdr.quadSpecRingLength = SWIZZLE_4_BYTE(i_qpmrHdr.quadSpecRingLength); - pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset); + io_qpmrHdr.quadCommonRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingOffset); + io_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength); + io_qpmrHdr.quadCommonOvrdOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdOffset); + io_qpmrHdr.quadCommonOvrdLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdLength); + io_qpmrHdr.quadSpecRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingOffset); + io_qpmrHdr.quadSpecRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength); + pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset); + pSgpeImgHdr->g_sgpe_scom_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_scom_offset); sgpeRings.dumpRings(); FAPI_DBG("SGPE Header Ring Details "); - FAPI_DBG("Common Ring Offset %d (0x%08x) ", + FAPI_DBG("Common Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset), SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset)); - FAPI_DBG("Instance Ring Offset %d (0x%08x) ", + FAPI_DBG("Instance Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset), SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset)); - FAPI_DBG( "< layoutRingsForSGPE"); return rc; } @@ -1787,7 +2055,7 @@ extern "C" attrVal ), "Error from FAPI_ATTR_SET for attribute ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET"); - FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08x", attrVal ); + FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); attrVal = (uint8_t*)(i_pChipHomer->ppmrRegion.l1BootLoader) - (uint8_t*)(i_pChipHomer); attrVal |= 0x80000000; @@ -1796,7 +2064,7 @@ extern "C" attrVal ), "Error from FAPI_ATTR_SET for attribute ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET"); - FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08x", attrVal ); + FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); fapi_try_exit: return fapi2::current_err; } @@ -1910,6 +2178,7 @@ extern "C" FAPI_INF("PGPE built"); + //Let us add Scan Rings to the image. uint8_t l_ringDebug = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE, FAPI_SYSTEM, @@ -1923,6 +2192,7 @@ extern "C" i_pBuf3, i_sizeBuf3 ); + //Extract all the rings for CME platform from HW Image and VPD ppeImgRc = getPpeScanRings( i_pImageIn, PLAT_CME, i_procTgt, @@ -1931,7 +2201,7 @@ extern "C" if( ppeImgRc ) { - FAPI_ERR( "failed to extract core scan rings rc = 0x%08x", ppeImgRc ); + FAPI_ERR( "failed to extract core scan rings rc = 0x%08X", ppeImgRc ); break; } @@ -1947,32 +2217,14 @@ extern "C" (RingDebugMode_t)l_ringDebug, l_iplPhase, i_imgType, - i_pRingOverride ? true : false ); + i_pRingOverride ); if( ppeImgRc ) { - FAPI_ERR("Failed to copy core Scan rings in HOMER rc 0x%08x", ppeImgRc ); + FAPI_ERR("Failed to copy core Scan rings in HOMER rc 0x%08X", ppeImgRc ); break; } - if( i_pRingOverride ) - { - FAPI_DBG("Extracting Override Rings for CME"); - l_ringData.iv_ringBufSize = i_sizeBuf1; - ppeImgRc = layoutCmeScanOverride( pChipHomer, - i_pRingOverride, - l_chipFuncModel, - l_ringData, - (RingDebugMode_t)l_ringDebug, - l_iplPhase, - i_imgType ); - - if( ppeImgRc ) - { - FAPI_INF("Did not find scan ring override for CME rc 0x%08x", ppeImgRc ); - } - } - l_ringData.iv_ringBufSize = i_sizeBuf1; ppeImgRc = getPpeScanRings( i_pImageIn, PLAT_SGPE, @@ -1988,6 +2240,7 @@ extern "C" // create a layout of rings in HOMER for consumption of SGPE ppeImgRc = layoutRingsForSGPE( pChipHomer, + i_pRingOverride, l_chipFuncModel, l_ringData, (RingDebugMode_t)l_ringDebug, @@ -1997,38 +2250,24 @@ extern "C" if( ppeImgRc ) { - FAPI_ERR("Failed to copy quad/ex Scan rings in HOMER rc 0x%08x", ppeImgRc ); + FAPI_ERR("Failed to copy quad/ex Scan rings in HOMER rc 0x%08X", ppeImgRc ); break; } - if( i_pRingOverride ) - { - FAPI_DBG("Extracting Override Rings for CME"); - l_ringData.iv_ringBufSize = i_sizeBuf1; - ppeImgRc = layoutSgpeScanOverride( pChipHomer, - i_pRingOverride, - l_chipFuncModel, - l_ringData, - (RingDebugMode_t)l_ringDebug, - l_iplPhase, - l_qpmrHdr, - i_imgType ); - - if( ppeImgRc ) - { - FAPI_INF("Did not find scan ring override for CME rc 0x%08x", ppeImgRc ); - } - } - - //Update CPMR Header area in HOMER with CME Image related information. - updateCpmrHeaderCME( pChipHomer ); - //Update CPMR Header with Scan Ring details - updateCpmrScanRing( pChipHomer ); + updateCpmrCmeRegion( pChipHomer ); //Update QPMR Header area in HOMER updateQpmrHeader( pChipHomer, l_qpmrHdr ); + //validate SRAM Image Sizes of PPE's + uint32_t sramImgSize = 0; + ppeImgRc = validateSramImageSize( pChipHomer, sramImgSize ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::IMG_EXCEED_SRAM_SIZE( ) + .set_BAD_IMG_SIZE( sramImgSize ), + "SRAM Image Size Exceeded Max Allowed Size" ); + //Finally update the attributes storing PGPE and SGPE's boot copier offset. retCode = updateGpeAttributes( pChipHomer, i_procTgt ); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C index 7f6366f31..3449250be 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.C @@ -239,14 +239,14 @@ RingBucket::RingBucket( PlatId i_plat, uint8_t* i_pRingStart, RingDebugMode_t i_ { ex_l3_refr_time, 0x19 }, { eq_repr, 0x15 }, - { ex_l3_repr, 0x20 }, - { ex_l3_repr, 0x21 }, - { ex_l2_repr, 0x20 }, - { ex_l2_repr, 0x21 }, - { ex_l3_refr_repr, 0x20 }, - { ex_l3_refr_repr, 0x21 }, - { ex_l3_refr_time, 0x20 }, - { ex_l3_refr_time, 0x21 }, + { ex_l3_repr, 0x1A }, + { ex_l3_repr, 0x1B }, + { ex_l2_repr, 0x1A }, + { ex_l2_repr, 0x1B }, + { ex_l3_refr_repr, 0x1A }, + { ex_l3_refr_repr, 0x1B }, + { ex_l3_refr_time, 0x1A }, + { ex_l3_refr_time, 0x1B }, }; @@ -561,6 +561,36 @@ const char* RingBucket::getRingName( RingID i_ringId ) } //------------------------------------------------------------------------- +void RingBucket::extractRing( void* i_ptr, uint32_t i_ringSize, uint32_t i_ringId ) +{ + do + { + if( SCAN_RING_NO_DEBUG == iv_debugMode ) + { + break; + } + + if( !i_ptr ) + { + break; + } + + uint8_t* pRing = (uint8_t*)(i_ptr); + uint16_t maxLines = i_ringSize / sizeof(uint64_t); + FAPI_DBG("Ring Id 0x%08x", i_ringId ); + + for( uint32_t ringId = 0; ringId < maxLines; ringId++ ) + { + FAPI_DBG("%02x %02x %02x %02x %02x %02x %02x %02x", + (*pRing ), *(pRing + 1), *(pRing + 2 ), *(pRing + 3 ), + *(pRing + 4 ), *(pRing + 5 ), *(pRing + 6 ), *(pRing + 7 ) ); + pRing = pRing + sizeof(uint64_t); + } + + } + while(0); +} +//------------------------------------------------------------------------- void RingBucket::dumpRings( ) { @@ -735,6 +765,9 @@ P9FuncModel::P9FuncModel( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP >& i_ iv_funcExes = iv_funcExes | (1 << (l_corePos >> 1) ); iv_funcQuads = iv_funcQuads | (1 << (l_corePos >> 2) ); } + + FAPI_DBG("functional core 0x%08x, Ex 0x%08x quad 0x%08x", + iv_funcCores, iv_funcExes, iv_funcQuads ); } //--------------------------------------------------------------------------- diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H index 73a2b7578..3e8980b4e 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_scan_ring_util.H @@ -263,6 +263,13 @@ class RingBucket */ void dumpOverrideRings(); + /** + * @brief prints a given ring for content debug + * @param i_ptr points to a work buffer containing ring. + * @param i_ringSize size of a ring. + * @param i_ringId ring id + */ + void extractRing( void* i_ptr, uint32_t i_ringSize, uint32_t i_ringId ); private: std::map<uint16_t, RingProfile> iv_cmnRingMap; std::map<uint16_t, RingProfile> iv_instRingMap; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index 1e000e921..66fd00afc 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -487,6 +487,13 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage, l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); + if( l_rc ) + { + MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016llx", + i_pir); + break; + } + MY_INF( " PIR 0x%016llx coreId %d threadid %d " " registerId %d", i_pir, coreId, threadId, i_regId ); diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H index 3901ae81a..a10d10e07 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H @@ -78,7 +78,8 @@ typedef enum STOP_SAVE_SCOM_INVALID_ADDRESS = 10, STOP_SAVE_SCOM_INVALID_CHIPLET = 11, STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED = 12, - STOP_SAVE_FAIL = 13, // for internal failure within firmware. + STOP_SAVE_INVALID_FUSED_CORE_STATUS = 13, + STOP_SAVE_FAIL = 14, // for internal failure within firmware. } StopReturnCode_t; /** diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H index ed34d7544..d660e5fb7 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_section_defines.H @@ -44,57 +44,57 @@ namespace stopImageSection //basic constants enum { - ONE_KB = 1024, - ONE_MB = ONE_KB * ONE_KB, - TWO_MB = 2 * ONE_MB, - MAX_CORE_SCOM_ENTRIES = 15, - MAX_EQ_SCOM_ENTRIES = 15, - MAX_L2_SCOM_ENTRIES = 16, - MAX_L3_SCOM_ENTRIES = 16, - MAX_CORE_ID_SUPPORTED = 23, - MAX_THREAD_ID_SUPPORTED = 3, - MAX_CACHE_SECTN_SIZE_PER_CHIPLET = - MAX_EQ_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES, +ONE_KB = 1024, +ONE_MB = ONE_KB * ONE_KB, +TWO_MB = 2 * ONE_MB, +MAX_CORE_SCOM_ENTRIES = 15, +MAX_EQ_SCOM_ENTRIES = 15, +MAX_L2_SCOM_ENTRIES = 16, +MAX_L3_SCOM_ENTRIES = 16, +MAX_CORE_ID_SUPPORTED = 23, +MAX_THREAD_ID_SUPPORTED = 3, +MAX_CACHE_SECTN_SIZE_PER_CHIPLET = + MAX_EQ_SCOM_ENTRIES + MAX_L2_SCOM_ENTRIES + MAX_L3_SCOM_ENTRIES, - // start offset for SPR register restore, core scom or cache scom register - // restore regions in homer image. - CORE_SCOM_SECTN_START = ( TWO_MB + ( 256 * ONE_KB )), //offset from start of chip HOMER - CACHE_SCOM_SECTN_START = ( ONE_MB + ( 128 * ONE_KB )), // start of cache section +// start offset for SPR register restore, core scom or cache scom register +// restore regions in homer image. +CORE_SCOM_SECTN_START = ( TWO_MB + ( 256 * ONE_KB )), //offset from start of chip HOMER +CACHE_SCOM_SECTN_START = ( ONE_MB + ( 128 * ONE_KB )), // start of cache section - //constants in HOMER's header area. - REGULAR_MODE = 0xAA, - FUSE_MODE = 0xBB, - HOMER_MAGIC_WORD = 0x484F4D4552312E30ll, - CACHE_CHIPLET_ID_MIN = 0x10, - CACHE_CHIPLET_ID_MAX = 0x15, - CORE_CHIPLET_ID_MIN = 0x20, - CORE_CHIPLET_ID_MAX = 0x37, - MAX_SPR_RESTORE_INST = 0x08, - SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), +//constants in HOMER's header area. +FUSED_MODE = 0xBB, +NONFUSED_MODE = 0xAA, +CPMR_MAGIC_WORD = 0x43504d525f312e30, +CACHE_CHIPLET_ID_MIN = 0x10, +CACHE_CHIPLET_ID_MAX = 0x15, +CORE_CHIPLET_ID_MIN = 0x20, +CORE_CHIPLET_ID_MAX = 0x37, +MAX_SPR_RESTORE_INST = 0x08, +SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), }; // all section sizes below are in bytes enum { - SCOM_ENTRY_SIZE = 16, - INTERRUPT_HANDLER_SIZE = 8 * ONE_KB, - THREAD_LAUNCHER_SIZE = 256, - THREAD_RESTORE_SECTN = 192, - THREAD_COMPLETION = 64, - THREAD_AREA_SIZE = ONE_KB, - THREAD_SECTN_SIZE = THREAD_RESTORE_SECTN + THREAD_COMPLETION, - CORE_SPR_SECTN_SIZE = ONE_KB, - L2_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES), - L3_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES ), - EQ_AREA = SCOM_ENTRY_SIZE * MAX_EQ_SCOM_ENTRIES, - MAX_SIZE_PER_CORE = 8 * ONE_KB, - SPR_RESTORE_PER_CHIP = ( MAX_SIZE_PER_CORE * - ( MAX_CORE_ID_SUPPORTED + 1)) + - ( INTERRUPT_HANDLER_SIZE + THREAD_LAUNCHER_SIZE), - SCOM_SIZE_PER_CORE = ( MAX_CORE_SCOM_ENTRIES + 1 ) * SCOM_ENTRY_SIZE, - SCOM_SIZE_PER_CHIP = SCOM_SIZE_PER_CORE * ( MAX_CORE_ID_SUPPORTED + 1), - SCOM_SIZE_PER_CACHE_CHIPLET = L2_AREA + L3_AREA + EQ_AREA - + SCOM_ENTRY_SIZE, +SCOM_ENTRY_SIZE = 16, +INTERRUPT_HANDLER_SIZE = 8 * ONE_KB, +THREAD_LAUNCHER_SIZE = 256, +THREAD_RESTORE_SECTN = 192, +THREAD_COMPLETION = 64, +THREAD_AREA_SIZE = ONE_KB, +THREAD_SECTN_SIZE = THREAD_RESTORE_SECTN + THREAD_COMPLETION, +CORE_SPR_SECTN_SIZE = ONE_KB, +L2_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES), +L3_AREA = (SCOM_ENTRY_SIZE * MAX_L2_SCOM_ENTRIES ), +EQ_AREA = SCOM_ENTRY_SIZE * MAX_EQ_SCOM_ENTRIES, +MAX_SIZE_PER_CORE = 8 * ONE_KB, +SPR_RESTORE_PER_CHIP = ( MAX_SIZE_PER_CORE * + ( MAX_CORE_ID_SUPPORTED + 1)) + + ( INTERRUPT_HANDLER_SIZE + THREAD_LAUNCHER_SIZE), +SCOM_SIZE_PER_CORE = ( MAX_CORE_SCOM_ENTRIES + 1 ) * SCOM_ENTRY_SIZE, +SCOM_SIZE_PER_CHIP = SCOM_SIZE_PER_CORE * ( MAX_CORE_ID_SUPPORTED + 1), +SCOM_SIZE_PER_CACHE_CHIPLET = L2_AREA + L3_AREA + EQ_AREA + + SCOM_ENTRY_SIZE, //size in byte ends }; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C index 0b89c164f..fa13eee64 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_util.C @@ -45,53 +45,53 @@ namespace stopImageSection /** * @brief Returns proc chip's fuse mode status. * @param i_pImage points to start of chip's HOMER image. - * @param o_fuseMode points to fuse mode information. + * @param o_fusedMode points to fuse mode information. * @return STOP_SAVE_SUCCESS if functions succeeds, error code otherwise. */ -StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fuseMode ) +StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fusedMode ) { - *o_fuseMode = false; - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; +*o_fusedMode = false; +StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - do +do +{ + if( !i_pImage ) { - if( !i_pImage ) - { - MY_ERR( "invalid pointer to HOMER image"); - l_rc = STOP_SAVE_ARG_INVALID_IMG; - break; - } + MY_ERR( "invalid pointer to HOMER image"); + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } - HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage; - HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler ); - - if( SWIZZLE_8_BYTE(HOMER_MAGIC_WORD) != pHomer->homerMagicNumber ) - { - MY_ERR("corrupt or invalid HOMER image location 0x%016llx", - pHomer->homerMagicNumber ); - break; - } + HomerSection_t* pHomerDesc = ( HomerSection_t* ) i_pImage; + HomerImgDesc_t* pHomer = (HomerImgDesc_t*)( pHomerDesc->interrruptHandler ); + if( SWIZZLE_8_BYTE(CPMR_MAGIC_WORD) != pHomer->cpmrMagicWord ) + { + MY_ERR("corrupt or invalid HOMER image location 0x%016llx", + SWIZZLE_8_BYTE(pHomer->cpmrMagicWord) ); + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } - if( (uint8_t) FUSE_MODE == pHomer->fuseModeStatus ) - { - *o_fuseMode = true; - break; - } + if( (uint8_t) FUSED_MODE == pHomer->fusedModeStatus ) + { + *o_fusedMode = true; + break; + } - if( (uint8_t) REGULAR_MODE == pHomer->fuseModeStatus ) - { - break; - } + if( (uint8_t) NONFUSED_MODE == pHomer->fusedModeStatus ) + { + break; + } - MY_ERR("Unexpected value 0x%08x for fuse mode. Bad or corrupt " - "HOMER location", pHomer->fuseModeStatus ); - l_rc = STOP_SAVE_FAIL; + MY_ERR("Unexpected value 0x%08x for fused mode. Bad or corrupt " + "HOMER location", pHomer->fuseModeStatus ); + l_rc = STOP_SAVE_INVALID_FUSED_CORE_STATUS ; - } - while(0); +} +while(0); - return l_rc; +return l_rc; } //---------------------------------------------------------------------- @@ -99,80 +99,81 @@ StopReturnCode_t isFusedMode( void* const i_pImage, bool* o_fuseMode ) StopReturnCode_t getCoreAndThread( void* const i_pImage, const uint64_t i_pir, uint32_t* o_pCoreId, uint32_t* o_pThreadId ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; +StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - do +do +{ + // for SPR restore using 'Virtual Thread' and 'Physical Core' number + // In Fused Mode: + // bit b28 and b31 of PIR give physical core and b29 and b30 gives + // virtual thread id. + // In Non Fused Mode + // bit 28 and b29 of PIR give both logical and physical core number + // whereas b30 and b31 gives logical and virtual thread id. + bool fusedMode = false; + uint8_t coreThreadInfo = (uint8_t)i_pir; + *o_pCoreId = 0; + *o_pThreadId = 0; + l_rc = isFusedMode( i_pImage, &fusedMode ); + + if( l_rc ) { - // for SPR restore using 'Virtual Thread' and 'Physical Core' number - // In Fuse Mode: - // bit b28 and b31 of PIR give physical core and b29 and b30 gives - // virtual thread id. - // In Non Fuse Mode - // bit 28 and b29 of PIR give both logical and physical core number - // whereas b30 and b31 gives logical and virtual thread id. - bool fuseMode = false; - uint8_t coreThreadInfo = (uint8_t)i_pir; - *o_pCoreId = 0; - *o_pThreadId = 0; - l_rc = isFusedMode( i_pImage, &fuseMode ); - - if( l_rc ) + MY_ERR(" Checking Fused mode. Read failed 0x%08x", l_rc ); + break; + } + + if( fusedMode ) + { + if( coreThreadInfo & FUSED_CORE_BIT1 ) + { + *o_pThreadId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT2 ) + { + *o_pThreadId += 1; + } + + if( coreThreadInfo & FUSED_CORE_BIT0 ) + { + *o_pCoreId = 2; + } + + if( coreThreadInfo & FUSED_CORE_BIT3 ) + { + *o_pCoreId += 1; + } + } + else + { + if( coreThreadInfo & FUSED_CORE_BIT0 ) { - MY_ERR(" Checking Fuse mode. Read failed 0x%08x", l_rc ); - break; + *o_pCoreId = 2; } - if( fuseMode ) + if ( coreThreadInfo & FUSED_CORE_BIT1 ) { - if( coreThreadInfo & FUSE_BIT1 ) - { - *o_pThreadId = 2; - } - - if( coreThreadInfo & FUSE_BIT2 ) - { - *o_pThreadId += 1; - } - - if( coreThreadInfo & FUSE_BIT0 ) - { - *o_pCoreId = 2; - } - - if( coreThreadInfo & FUSE_BIT3 ) - { - *o_pCoreId += 1; - } + *o_pCoreId += 1; } - else + + if( coreThreadInfo & FUSED_CORE_BIT2 ) { - if( coreThreadInfo & FUSE_BIT0 ) - { - *o_pCoreId = 2; - } - - if ( coreThreadInfo & FUSE_BIT1 ) - { - *o_pCoreId += 1; - } - - if( coreThreadInfo & FUSE_BIT2 ) - { - *o_pThreadId = 2; - } - - if( coreThreadInfo & FUSE_BIT3 ) - { - *o_pThreadId += 1; - } + *o_pThreadId = 2; } - //quad field is not affected by fuse mode - *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); + if( coreThreadInfo & FUSED_CORE_BIT3 ) + { + *o_pThreadId += 1; + } } - while(0); - return l_rc; + MY_INF("Core Type %s", fusedMode ? "Fused" : "Un-Fused" ); + //quad field is not affected by fuse mode + *o_pCoreId += 4 * (( coreThreadInfo & 0x70 ) >> 4 ); +} +while(0); + +return l_rc; } #ifdef __cplusplus diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml index 27215fda0..8ed0bb58f 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml @@ -140,4 +140,14 @@ </callout> </hwpError> <!-- *********************************************************************** --> + <hwpError> + <rc>RC_IMG_EXCEED_SRAM_SIZE</rc> + <description>Size of image exceeded the SRAM size of platform</description> + <ffdc>BAD_IMG_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> </hwpErrors> |
