SGPE and CME scanning integration

- Enable FAPI2 targets (move to .C)
- Add/enhance hcode_image_build and wrapper tracing for debug
- Fix CME boot to match the layout of CPMR with common scanning
- Add internal target creation to initf for testing
- Update p9_hcode_image_defines with realistic sizes.
- Cleaned up some wrappers for better debug and tracing
- Cleaned up some extraneous defines
- Fixed vector constructor functionality.
    - Removed -gc-sections from stop_gpe.mk so that constructor code remained
    - Fixed hcode_image_build in its adding of scan rings to not overlay the
      Hcode data region.
- Fix quad based creation of local target
- Redid boot_loader to properly deal with scan ring sections
- Fix boot copier header dependency
- Moved SGPE Hcode space to 38KB to deal with present size;  Made SGPE total
  OCC SRAM allocation 80KB for now.  This growth is due to fapi2 required
  vector support (4 x 128KB) plus target init (1KB) plus scan ring allocation
  per latest assumptions. The FAPI2 elements will be readdressed later.
- Remove skip arrayinit/scan0 from istep15_hack and into EPM_TUNING
- Some bug fixes in hcode_image_defines to get proper common ring offsets
  in SGPE header as well as proper placement of common rings in image
- Changes from Prasad with putrings updates
- Removed break points to call broadside scans in CME and SGPE codes.
- Added Prasad's changes for putring for CME and SGPE.
- Increased thread stack size
- Rebased and commented out memory faulting code for now
- Removed call in p9_pm_stop_gpe_init to ppe_state due to HB strings (for now)
- Fix SGPE_ALLOCATED_SIZE
- Boot loader fix
- Pulled in PK PBA context bug fix as this corrupts the PBASLVCTL0 and thus
  memory accesses
- Make CPMR and CME Header values have maximums. Add check to not allow overrun
- Hcode Image Wrapper update
- CME header debug output

Change-Id: I71718485ff3192f3723fdfa03b8bc6f558ef120e
RTC: 136960
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27421
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30629
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 181 insertions, 75 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index 6e4327057..2f95a697a 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -46,7 +46,6 @@
 namespace p9_hcodeImageBuild
 {
 #endif //__PPE_PLAT
-
 #endif //__ASSEMBLER__
 
 // Constants used in both C++ and Assembler/Linker code
@@ -280,14 +279,15 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE);
 #endif
 
 #ifndef __ASSEMBLER__
+
 /**
  * @brief   summarizes constants associated with hcode image build.
  */
 enum
 {
+    HALF_KB                     = 512,
     ONE_KB                      = 1024,
     ONE_MB                      = 1024 * 1024,
-    HALF_KB                     = 512,
     HARDWARE_IMG_SIZE           = ONE_MB,
     OCC_HOST_AREA_SIZE          = ONE_MB,
     HOMER_OCC_REGION_NUM        = 0,
@@ -295,70 +295,122 @@ enum
     HOMER_CMPR_REGION_NUM       = 2,
     HOMER_PPMR_REGION_NUM       = 3,
     MAX_CORES_PER_CHIP          = 24,
+    THREADS_PER_CORE            = 4,
     MAX_CME_PER_CHIP            = 12,
+    MAX_CACHE_CHIPLETS          = 6,
+    CACH0_CHIPLET_ID            = 0x10,
     CORE0_CHIPLET_ID            = 0x20,
     PAD_OPCODE                  = 0x00000200,   //ATTN Opcode
     PPE_RESERVE_AREA            = 0x200,
     FUSE_STATE                  = 0xAA,
     UNFUSE_STATE                = 0xBB,
     PK_DBG_PTR_AREA_SIZE        = 64,
+    SCOM_ENTRY_SIZE             = 16,           // 4B pad, 4B address, 8B data
 
-    // QPMR
+    //---- QPMR  ----
     QPMR_OFFSET                 = HOMER_QPMR_REGION_NUM * ONE_MB,
+
+    //** Boot Loaders
     SGPE_LVL_1_BOOT_LOAD_SIZE   = ONE_KB,
     SGPE_LVL_2_BOOT_LOAD_SIZE   = ONE_KB,
+
+    //** Hcode
     SGPE_INT_VECT               = 384,
+    //SGPE_IMG_HEADER             = 64,
     SGPE_IMG_HEADER             = sizeof(sgpeHeader_t),
-    SGPE_HCODE_SIZE             = 32 * ONE_KB, // FIXME RTC 155018 Revisit after Hcode optimization
+    SGPE_DBG_PTR_AREA_SIZE      = 64,
+    //SGPE_HCODE_SIZE             = 32 * ONE_KB, // FIXME RTC 155018 Revisit after Hcode optimization
+    SGPE_HCODE_SIZE             = 38 * ONE_KB,  // @todo RTC 158543 Reallocate space
+
     SGPE_EXE_SIZE               = (SGPE_HCODE_SIZE - ( SGPE_INT_VECT +
                                    SGPE_IMG_HEADER + PK_DBG_PTR_AREA_SIZE )),
-    SGPE_COMMON_RING            = 13  * ONE_KB, // Common rings (10KB) + Override rings(3KB)
-    CACHE_INST_SPECIFIC_SIZE    = 19  * ONE_KB,
-    CACHE_SCOM_RESTORE_SIZE     = 6 * ONE_KB, //4488B rounded to 6KB
+
+    SGPE_ALLOCATED_SIZE         = SGPE_HCODE_SIZE,   // @todo RTC 158543 Reallocate space (collapse??)
+
+    //** Scan
+    //SGPE_COMMON_RING            = 13  * ONE_KB, // Common rings (10KB) + Override rings(3KB)
+    SGPE_COMMON_RING_SIZE       = 13 * ONE_KB,  // 400B * 9 rings * 3 types (base, RL, CC)
+    SGPE_OVERRIDE_RING_SIZE     = 3 * ONE_KB,   // 300B * 9 rings
+
+    CACHE_INST_SPECIFIC_SIZE    = (3 * ONE_KB) + HALF_KB, // per cache, 1KB/ring x 5 rings/cache
+    CACHE_SPECIFIC_RING_SIZE    = MAX_CACHE_CHIPLETS * CACHE_INST_SPECIFIC_SIZE,
     SGPE_INSTRUMENTATION_SIZE   = 2 * ONE_KB,
-    MAX_CACHE_CHIPLET           = 6,
-    CACH0_CHIPLET_ID            = 0x10,
 
-    SGPE_MAX_AREA_SIZE          = 64 * ONE_KB,
+    //** SCOM
+    NUM_CACHE_SCOM_REGS         = 47 + 1,       // 16 L2 repr, 16 L3 repr, 15 non-repr, 1 NULL
+    CACHE_SCOM_RESTORE_SIZE     = MAX_CACHE_CHIPLETS * NUM_CACHE_SCOM_REGS * SCOM_ENTRY_SIZE,
+
+    CACHE_SCOM_START            = 128 * ONE_KB, // HOMER offset from QPMR
+
+    //** OCC SRAM Allocation
+    SGPE_MAX_AREA_SIZE          = 80 * ONE_KB,  // Allocation within the OCC SRAM
+    SGPE_RESERVE_SIZE           = SGPE_MAX_AREA_SIZE -
+                                  ( SGPE_HCODE_SIZE +
+                                    SGPE_COMMON_RING_SIZE +
+                                    CACHE_SCOM_RESTORE_SIZE +
+                                    SGPE_OVERRIDE_RING_SIZE +
+                                    CACHE_SCOM_RESTORE_SIZE),
 
-    // CPMR
+    //---- CPMR ----
     CPMR_OFFSET                 = HOMER_CMPR_REGION_NUM * ONE_MB,
+
+    //** Self Restore
     THREAD_LAUNCHER_SIZE        = 256,
     CORE_INT_AREA               = 8 * ONE_KB,
     SELF_REST_SIZE              = CORE_INT_AREA + THREAD_LAUNCHER_SIZE,
-    CORE_RESTORE_SIZE           = 192 * ONE_KB,
+    CORE_RESTORE_SIZE           = ((2 * ONE_KB) * THREADS_PER_CORE) * MAX_CORES_PER_CHIP,
+
+    //** SCOM
     CORE_SCOM_START             = (256 * ONE_KB),
-    CORE_SCOM_RES_SIZE          = 6 * ONE_KB,
+    CORE_SCOM_RESTORE_SIZE      = SCOM_ENTRY_SIZE * 16, // (15 registers + 1 NULL) per core
+    CORE_SCOM_RES_SIZE          = CORE_SCOM_RESTORE_SIZE * MAX_CORES_PER_CHIP,
+    CME_SCOM_AREA               = CORE_SCOM_RESTORE_SIZE * 2, // 2 cores
+    SCOM_AREA_PER_CME           =  HALF_KB, // 256(ea ) * 2( CORES PER CME) (???)
+
+    //** Hcode
     CME_INT_VECTOR_SIZE         = 384,
+    CME_IMG_HEADER_SIZE         = 64,
     CPMR_CME_HCODE_OFFSET       = (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
-    CME_HCODE_SIZE              = (25 * ONE_KB) + HALF_KB,
+    CME_HCODE_SIZE              = (27 * ONE_KB) + HALF_KB,
+
+    //** Scan
     CORE_COMMON_RING_SIZE       = 3  * ONE_KB, // common ring( 2KB) + common overrides (1KB)
-    CORE_SPECIFIC_RING          = 2  * ONE_KB,
-    SCOM_AREA_PER_CME           =  HALF_KB, // 256(ea ) * 2( CORES PER CME)
-    QUAD_PSTATE_SIZE            = HALF_KB,
-    INSTRUMENTATION_COUNTERS    = HALF_KB,
-    CME_SRAM_HCODE_OFFSET       = 0x00,
-    CORE_RESERVE_SIZE           =
-        CORE_SCOM_START - ( CORE_RESTORE_SIZE + CME_HCODE_SIZE + CORE_COMMON_RING_SIZE + QUAD_PSTATE_SIZE  ),
-
-    CME_REGION_START            =  (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
-    CME_INST_SPEC_RING_START    =  (300 * ONE_KB ) ,
-    RESERVE_CME_RING_AREA       =  ( CME_INST_SPEC_RING_START  - ( CME_REGION_START +
+    CORE_SPECIFIC_RING          = 2 * ONE_KB,   // per core
+    CORE_OVERRIDE_RING          = 1 * ONE_KB,   // common for all cores
+    QUAD_PSTATE_SIZE            = HALF_KB,      // common for all cores
+    CME_INSTRUMENTATION_SIZE    = HALF_KB,      // per CME
+    INSTRUMENTATION_COUNTERS    = HALF_KB,      // (???)
+
+    CORE_RESERVE_SIZE           = CORE_SCOM_START -
+                                  ( CORE_RESTORE_SIZE +
+                                    CME_HCODE_SIZE +
+                                    CORE_COMMON_RING_SIZE +
+                                    QUAD_PSTATE_SIZE  ),
+
+    CME_SRAM_HCODE_OFFSET       = 0x00, //(???)
+    CME_REGION_START            = (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
+    CME_INST_SPEC_RING_START    = 300 * ONE_KB,
+    RESERVE_CME_RING_AREA       = ( CME_INST_SPEC_RING_START  -
+                                    (CME_REGION_START +
                                      CME_HCODE_SIZE +
                                      CORE_COMMON_RING_SIZE +
                                      QUAD_PSTATE_SIZE)),
-    CME_BLOCK_READ_LEN          =  32,
-    CME_BLK_SIZE_SHIFT          =  0x05,
-    CACHE_SCOM_START            =  128 * ONE_KB,
+    CME_BLOCK_READ_LEN          = 32,
+    CME_BLK_SIZE_SHIFT          = 0x05,
 
     // PPMR
+
+    //** Boot Loaders
     PGPE_LVL_1_BOOT_LOAD_SIZE   = ONE_KB,
     PGPE_LVL_2_BOOT_LOAD_SIZE   = ONE_KB,
-    PGPE_INT_VECTOR             =  384,
-    PGPE_HCODE_SIZE             =  32 * ONE_KB,
-    PGPE_PARAM_BLOCK_SIZE       =  4 * ONE_KB,
-    PSTATE_OUTPUT_TABLE         =  4 * ONE_KB,
-    IGNORE_CHIPLET_INSTANCE     =  0xFF,
+    PGPE_INT_VECTOR             = 384,
+    PGPE_HCODE_SIZE             = 30 * ONE_KB,
+    PGPE_PARAM_BLOCK_SIZE       = 8 * ONE_KB,  //Global and OCC PPB
+    PSTATE_OUTPUT_TABLE         = 8 * ONE_KB,
+    IGNORE_CHIPLET_INSTANCE     = 0xFF,
+
+    PGPE_MAX_AREA_SIZE          = 48 * ONE_KB, // @todo RTC 158543 Reallocate space
+
 };
 
 /**
@@ -408,8 +460,10 @@ typedef struct
     uint8_t imgHeader[sizeof(sgpeHeader_t)];
     uint8_t debugPtrs[PK_DBG_PTR_AREA_SIZE];
     uint8_t hcode[SGPE_EXE_SIZE];
-    uint8_t commonRings[SGPE_COMMON_RING];
-    uint8_t cacheSpecificRing[CACHE_INST_SPECIFIC_SIZE];
+    uint8_t commonRings[SGPE_COMMON_RING_SIZE];
+    uint8_t cacheSpecificRing[CACHE_SPECIFIC_RING_SIZE];
+    uint8_t overrideRings[SGPE_OVERRIDE_RING_SIZE];
+    uint8_t cacheScomRestore[CACHE_SCOM_RESTORE_SIZE];
 } SgpeLayout_t;
 
 typedef union CPMRSelfRestoreLayout
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 4aaccd5d8..afe0d4868 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -190,7 +190,9 @@ extern "C"
         pCpmrHdr->coreScomLength         =  SWIZZLE_4_BYTE((CORE_SCOM_RES_SIZE >> CME_BLK_SIZE_SHIFT));
 
         FAPI_INF("CPMR CME Hcode");
-        FAPI_INF("  CME Offset              = 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
+        FAPI_INF("  CME Offset              = 0x%08X, Header value 0x%08X (Real offset / 32)",
+                 SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32,
+                 SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
         FAPI_INF("  CME Size                = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));
         FAPI_INF("  CME SCOM Offset         = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset) );
         FAPI_INF("  CME SCOM Length         = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength) );
@@ -215,7 +217,6 @@ extern "C"
                                             (uint8_t*) &i_pChipHomer->cpmrRegion;
         pCpmrHdr->cmeCommonRingOffset    =  SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset);
 
-        pCpmrHdr->cmeCommonRingLength    =  pCmeHdr->g_cme_common_ring_length;
         pCpmrHdr->coreSpecRingOffset     =  SWIZZLE_4_BYTE(CME_INST_SPEC_RING_START);
         pCpmrHdr->coreSpecRingLength     =  pCmeHdr->g_cme_max_spec_ring_length; // already swizzled
 
@@ -224,23 +225,32 @@ extern "C"
         //hcode image build there are holes between various section of image say common and instance ring.
         pCpmrHdr->cmeImgLength            =     SWIZZLE_4_BYTE( CME_HCODE_SIZE );
         pCpmrHdr->cmeCommonRingLength     =     SWIZZLE_4_BYTE( CORE_COMMON_RING_SIZE );
-        pCpmrHdr->cmePstateLength         =     SWIZZLE_4_BYTE( QUAD_PSTATE_SIZE);
+        pCmeHdr->g_cme_common_ring_length  =    pCpmrHdr->cmeCommonRingLength;
+        pCpmrHdr->cmePstateLength         =     0;   // This needs to be fixed later.
         pCpmrHdr->cmePstateOffset         =     SWIZZLE_4_BYTE(i_pChipHomer->cpmrRegion.quadPstateArea -
                                                 (uint8_t*)&i_pChipHomer->cpmrRegion);
 
         FAPI_INF("CPMR CME Scan Rings");
-        FAPI_INF("  CME CMN Ring Offset     = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset) );
-        FAPI_INF("  CME CMN Ring Length     = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength) );
-        FAPI_INF("  CME Spec Ring Length    = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength) );
+        FAPI_INF("  CME Cmn Ring Offset  = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset) );
+        FAPI_INF("  CME Cmn Ring Length  = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength) );
+        FAPI_INF("  CME Spc Ring Offset  = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)  );
+        FAPI_INF("  CME Spc Ring Length  = 0x%08x", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)  );
 
         FAPI_INF("CME Header Scan Rings");
-        FAPI_INF("  CME Cmn Ring Offset         = 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset));
-        FAPI_INF("  CME Cmn Ring Length         = 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length) );
-        FAPI_INF("  Core Instance Ring Offset   = 0x%08x (Real offset / 32) ",
+        FAPI_INF("  Magic Num       = 0x%16lX", SWIZZLE_8_BYTE(pCmeHdr->g_cme_magic_number));
+        FAPI_INF("  HC Offset       = 0x%08X",  SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset));
+        FAPI_INF("  HC Size         = 0x%08X",  SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length));
+        FAPI_INF("  CR Offset       = 0x%08X",  SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset));
+        FAPI_INF("  CR Size         = 0x%08X",  SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length));
+        FAPI_INF("  CPMR Phy Add    = 0x%016lX", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr));
+        FAPI_INF("  PS Offset       = 0x%08X",  SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset));
+        FAPI_INF("  PS Size         = 0x%08X",  SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length));
+        FAPI_INF("  SR Offset       = 0x%08X, Header value 0x%08X (Real offset / 32)",
+                 SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset) * 32,
                  SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset));
-        FAPI_INF("  Core Instance Ring Length   = 0x%08x (Real length / 32)",
+        FAPI_INF("  SR Size         = 0x%08X, Header value 0x%08X (Real offset / 32)",
+                 SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) * 32,
                  SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) );
-        FAPI_INF("  Core Spec Ovrd Ring Offset  = 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_ovrd_offset ));
 
     }
 
@@ -266,7 +276,9 @@ extern "C"
         FAPI_INF("CPMR SR");
         FAPI_INF("  Fuse Mode = 0x%08X CME Image Flag = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->fuseModeStatus),
                  SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags));
-        FAPI_DBG("  Offset    = 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
+        FAPI_DBG("  Offset    = 0x%08X, Header value 0x%08X (Real offset / 32)",
+                 SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32,
+                 SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
         FAPI_DBG("  Size      = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));
 
         FAPI_INF("< updateCpmrHeaderSR");
@@ -290,7 +302,7 @@ extern "C"
         //hcode image build there are holes between various section of image say common and instance ring.
 
         pQpmrHdr->sgpeImgLength         =   SWIZZLE_4_BYTE(SGPE_HCODE_SIZE);
-        pQpmrHdr->quadCommonRingOffset  =   SWIZZLE_4_BYTE(SGPE_COMMON_RING);
+        pQpmrHdr->quadCommonRingOffset  =   SWIZZLE_4_BYTE(SGPE_COMMON_RING_SIZE);
         pQpmrHdr->quadSpecRingLength    =   SWIZZLE_4_BYTE(CACHE_INST_SPECIFIC_SIZE);
 
         memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) );
@@ -308,8 +320,21 @@ extern "C"
         FAPI_INF("  BL Size         = 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength));
         FAPI_INF("  HC Offset       = 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset));
         FAPI_INF("  HC Size         = 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength));
-        FAPI_DBG("  Cmn Ring Offset = 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) );
-        FAPI_DBG("  Cmn Ring Length = 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) );
+        FAPI_INF("  Cmn Ring Offset = 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) );
+        FAPI_INF("  Cmn Ring Length = 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) );
+        FAPI_INF("  Spc Ring Offset = 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) );
+        FAPI_INF("  Spc Ring Length = 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) );
+
+        sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.imgHeader;
+        FAPI_INF("SGPE Header");
+        FAPI_INF("  Magic Num       = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number));
+        FAPI_INF("  Reset Addr      = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_reset_address));
+        FAPI_INF("  IVPR Addr       = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_ivpr_address));
+        FAPI_INF("  Build Date      = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_date));
+        FAPI_INF("  Version         = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_ver));
+        FAPI_INF("  CR OCC Offset   = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_occ_offset));
+        FAPI_INF("  SR OCC Offset   = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_spec_ring_occ_offset));
+        FAPI_INF("  SCOM Offset     = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_scom_offset));
 
         return rc;
     }
@@ -427,24 +452,26 @@ extern "C"
                 break;
             }
 
+            o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE;
+            o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(ppeSection.iv_size);  // Endianess already accounted for
+
             FAPI_DBG("SGPE Hcode       QPMR Offset = 0x%08X, Size = 0x%08X",
                      SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset),
                      SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgLength));
 
-            o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_LVL_2_BOOT_LOAD_SIZE;
-
-            //let us take care of endianess now.
-            o_qpmrHdr.sgpeImgLength       = SWIZZLE_4_BYTE(ppeSection.iv_size);
-            o_qpmrHdr.bootLoaderOffset    = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset);
+            //let us take care of endianess now
             o_qpmrHdr.bootCopierOffset    = SWIZZLE_4_BYTE(o_qpmrHdr.bootCopierOffset);
-            o_qpmrHdr.sgpeImgOffset       = SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset);
+            o_qpmrHdr.bootLoaderOffset    = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset);
             o_qpmrHdr.bootLoaderLength    = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderLength);
+            o_qpmrHdr.sgpeImgOffset       = SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset);
+            o_qpmrHdr.sgpeImgLength       = SWIZZLE_4_BYTE(ppeSection.iv_size);
+
 
             //FIXME Need to confirm it
             o_qpmrHdr.quadSpecScomOffset  = SWIZZLE_4_BYTE(CACHE_SCOM_START);
 
             sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.imgHeader;
-            pImgHdr->g_sgpe_cmn_ring_occ_offset = o_qpmrHdr.sgpeImgLength;
+            pImgHdr->g_sgpe_cmn_ring_occ_offset = SWIZZLE_4_BYTE(SGPE_ALLOCATED_SIZE);
 
             FAPI_INF("SGPE Header");
             FAPI_INF("  Magic Num     = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number));
@@ -453,21 +480,21 @@ extern "C"
             FAPI_INF("  Build Date    = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_date));
             FAPI_INF("  Version       = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_ver));
             FAPI_INF("  CR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_occ_offset));
-            FAPI_INF("  SR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_spec_ring_occ_offset));
-            FAPI_INF("  SCOM Offset   = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_scom_offset));
+//            FAPI_INF("  SR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_spec_ring_occ_offset));
+//            FAPI_INF("  SCOM Offset   = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_scom_offset));
 
             //updating SGPE Image header in HOMER
             // FIXME Need to handle fields related SCOM OCC offsets
 
-            uint32_t regionLimit = CACHE_SCOM_RESTORE_SIZE >> 2;
-
-            FAPI_DBG("Padding SCOM region starting for 0x%08X bytes", CACHE_SCOM_RESTORE_SIZE);
-            uint32_t l_fillPattern = PAD_OPCODE;
-
-            for( uint32_t wordCnt = 0; wordCnt < regionLimit; wordCnt++ )
-            {
-                memcpy( i_pChipHomer->qpmrRegion.cacheScomRegion, &l_fillPattern, sizeof(uint32_t) );
-            }
+//             uint32_t regionLimit = CACHE_SCOM_RESTORE_SIZE >> 2;
+//
+//             FAPI_DBG("Padding SCOM region starting for 0x%08X bytes", CACHE_SCOM_RESTORE_SIZE);
+//             uint32_t l_fillPattern = PAD_OPCODE;
+//
+//             for( uint32_t wordCnt = 0; wordCnt < regionLimit; wordCnt++ )
+//             {
+//                 memcpy( i_pChipHomer->qpmrRegion.cacheScomRegion, &l_fillPattern, sizeof(uint32_t) );
+//             }
         }
         while(0);
 
@@ -621,7 +648,20 @@ extern "C"
                 // Note: Only the *memory* addresses are updated
                 cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeBin.elements.imgHeader;
                 pImgHdr->g_cme_hcode_offset =  SWIZZLE_4_BYTE(CME_SRAM_HCODE_OFFSET);
-                pImgHdr->g_cme_hcode_length =  SWIZZLE_4_BYTE(ppeSection.iv_size);
+
+                uint32_t cme_hcode_length = ppeSection.iv_size;
+                FAPI_INF("  CME Hcode Actual Size    = 0x%08X", cme_hcode_length);
+
+                if (cme_hcode_length > CME_HCODE_SIZE)
+                {
+                    FAPI_ERR("CME Hcode greater than allocated space.  Allocated = 0x%08X; Actual Size = 0x%08X",
+                             CME_HCODE_SIZE, cme_hcode_length);
+                    retCode = BUILD_FAIL_CME_HCODE;
+                    break;
+                }
+
+                pImgHdr->g_cme_hcode_length =  SWIZZLE_4_BYTE(CME_HCODE_SIZE);
+                FAPI_INF("  CME Hcode Allocated Size = 0x%08X", CME_HCODE_SIZE);
 
                 //Populating common ring offset here. So, that other scan ring related field can be updated.
                 pImgHdr->g_cme_common_ring_offset =  SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset) +
@@ -899,7 +939,7 @@ extern "C"
             if( tempBufLength == io_bufLength )
             {
                 FAPI_DBG(" %s Overrides not found for %s",
-                         ((i_instanceId == IGNORE_CHIPLET_INSTANCE ) ? "Common" : "Inst Speccific"),
+                         ((i_instanceId == IGNORE_CHIPLET_INSTANCE ) ? "Common" : "Inst Specific"),
                          ((PLAT_CME == i_platId) ? "CME" : "SGPE" ));
 
                 io_bufLength = 0;
@@ -1119,6 +1159,9 @@ extern "C"
                         SWIZZLE_4_BYTE(SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) +
                                        SWIZZLE_4_BYTE(o_qpmr.quadCommonRingLength));
 
+                    FAPI_DBG(" SGPE Image Header - specific scan ring offset 0x%08x",
+                             SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset));
+
                     //FIXME Assigning maximum size for now to facilitate bootloader. Eventually design shall be changed
                     //to eliminate max size allocation for each section say hcode or rings. Each section shall be
                     //packed next to each other.
@@ -1363,7 +1406,7 @@ extern "C"
                     pCmeImgHdr->g_cme_core_spec_ring_offset = tempLength;
                     pCmeImgHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(SWIZZLE_4_BYTE(pCmeImgHdr->g_cme_core_spec_ring_offset) +
                                                     SWIZZLE_4_BYTE(pCmeImgHdr->g_cme_max_spec_ring_length));
-                    pCmeImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(SCOM_AREA_PER_CME);
+                    pCmeImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CME_SCOM_AREA);
                 }
             }
         }
@@ -1482,8 +1525,6 @@ extern "C"
             FAPI_DBG("HOMER base address 0x%016lX", cpmrPhyAdd );
             ppeImgRc = buildCmeImage( i_pImageIn, pChipHomer, i_imgType, cpmrPhyAdd );
 
-            ppeImgRc = IMG_BUILD_SUCCESS;
-
             FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ),
                          fapi2::CME_BUILD_FAIL()
                          .set_CME_FAIL_SECTN( ppeImgRc ),
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
index 9cbbdeb52..a6d8ca549 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
@@ -60,6 +60,7 @@
 #include <p9_pm_stop_gpe_init.H>
 #include <p9_pm_pba_init.H>
 #include <p9_pm_pfet_init.H>
+//#include <p9_ppe_state.H>  @todo RTC 147996 to incorporate PPE state removing strings.
 
 
 // ----------------------------------------------------------------------
@@ -76,6 +77,11 @@ static const uint32_t SGPE_POLLTIME_MS      = 20;       // Guess at this time
 static const uint32_t SGPE_POLLTIME_MCYCLES = 2;        // Guess at this time
 static const uint32_t TIMEOUT_COUNT = SGPE_TIMEOUT_MS / SGPE_POLLTIME_MS;
 
+static const uint64_t GPE3_BASE_ADDRESS = 0x00066010;
+static const uint64_t SGPE_BASE_ADDRESS = GPE3_BASE_ADDRESS;
+
+
+
 // -----------------------------------------------------------------------------
 //  Function prototypes
 // -----------------------------------------------------------------------------
@@ -182,6 +188,8 @@ fapi2::ReturnCode stop_gpe_init(
     fapi2::buffer<uint64_t> l_occ_flag;
     fapi2::buffer<uint64_t> l_xcr;
     fapi2::buffer<uint64_t> l_xsr;
+    fapi2::buffer<uint64_t> l_iar;
+    fapi2::buffer<uint64_t> l_ir;
     fapi2::buffer<uint64_t> l_ivpr;
     fapi2::buffer<uint64_t> l_slave_cfg;
     uint32_t                l_ivpr_offset;
@@ -228,13 +236,16 @@ fapi2::ReturnCode stop_gpe_init(
     {
         FAPI_TRY(getScom(i_target, PU_OCB_OCI_OCCFLG_SCOM, l_occ_flag));
         FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIXSR_SCOM, l_xsr));
-        FAPI_DBG("   Poll content: OCC Flag: 0x%16llX; XSR: 0x%16llX Timeout: %d",
+        FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIIAR_SCOM, l_iar));
+        FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIIR_SCOM, l_ir));
+        FAPI_DBG("   Poll content: OCC Flag: 0x%16llX; XSR: 0x%16llX  IAR: 0x%16llX IR: 0x%16llX Timeout: %d",
                  l_occ_flag,
                  l_xsr,
+                 l_iar,
+                 l_ir,
                  l_timeout_in_MS);
         fapi2::delay(SGPE_POLLTIME_MS * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000);
 
-
     }
     while((!((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() == 1) &&
              (l_xsr.getBit<p9hcd::HALTED_STATE>() == 0))) &&