Chip ID fixes for 64GB enablement

Change-Id: Iecb3ae84b38c99d4b94eee0c12d0cce1ddd88ebc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46020
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: JEREMY R. NEATON <jrneaton@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46085
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 48 insertions, 36 deletions

diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C
index ca84a7a12..125fe180d 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_funcs.C
@@ -105,13 +105,6 @@ fapi2::ReturnCode mss_ddr4_invert_mpr_write( const fapi2::Target<fapi2::TARGET_T
 
         FAPI_INF( "Stack Type in mss_ddr4_invert_mpr_write : %d\n", l_dram_stack[0][0]);
 
-        if (l_dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
-        {
-            FAPI_INF( "=============  Got in the 3DS stack loop =====================\n");
-            FAPI_TRY(l_csn_8.clearBit(2, 2));
-            FAPI_TRY(l_csn_8.clearBit(6, 2));
-            // COMMENT IN LATER!!!!!! rc_num = rc_num | l_cke_4.clearBit(1));
-        }
 
         FAPI_TRY(mss_ccs_inst_arry_0( i_target_mba,
                                       l_ccs_inst_cnt,
@@ -162,6 +155,14 @@ fapi2::ReturnCode mss_ddr4_invert_mpr_write( const fapi2::Target<fapi2::TARGET_T
 
                     FAPI_TRY(l_csn_8.setBit(0, 8));
                     FAPI_TRY(l_csn_8.clearBit(l_rank_number + 4 * l_dimm));
+
+                    if (l_dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
+                    {
+                        FAPI_INF( "=============  Got in the 3DS stack loop =====================\n");
+                        FAPI_TRY(l_csn_8.clearBit(2, 2)); // Clearing CKE caused issues here.
+                        FAPI_TRY(l_csn_8.clearBit(6, 2));
+                    }
+
                     FAPI_TRY(l_address_16.clearBit(0, 16));
 
                     // MRS CMD to CMD spacing = 12 cycles
@@ -526,14 +527,17 @@ fapi2::ReturnCode mss_create_rcd_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA
                     if(l_stack_height == 8)
                     {
                         l_rcd_cntl_word_8_9 = 0x00;
+                        l_rcd_cntl_word_Bx[l_port][l_dimm] = 0x00;
                     }
                     else if(l_stack_height == 4)
                     {
                         l_rcd_cntl_word_8_9 = 0x10;
+                        l_rcd_cntl_word_Bx[l_port][l_dimm] = 0x04;
                     }
                     else if(l_stack_height == 2)
                     {
                         l_rcd_cntl_word_8_9 = 0x20;
+                        l_rcd_cntl_word_Bx[l_port][l_dimm] = 0x06;
                     }
                     //weird, we shouldn't have 1H stacks
                     else
@@ -542,7 +546,6 @@ fapi2::ReturnCode mss_create_rcd_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA
                     }
                 }
             }
-
             //LR DIMM and 4 ranks
             else if(l_dimm_type_u8 == fapi2::ENUM_ATTR_CEN_EFF_DIMM_TYPE_LRDIMM
                     && l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4)
@@ -553,6 +556,7 @@ fapi2::ReturnCode mss_create_rcd_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA
             else
             {
                 l_rcd_cntl_word_8_9 = 0x30;
+                l_rcd_cntl_word_Bx[l_port][l_dimm] = 0x07;
             }
 
             // RDIMM Operating Speed Control Word
@@ -618,14 +622,9 @@ fapi2::ReturnCode mss_create_rcd_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA
             // DIMM Configuration Control words
             FAPI_TRY(l_data_buffer_8.clearBit(0, 8));
 
-            if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 )
-            {
-                FAPI_TRY(l_data_buffer_8.setBit(3)); // Direct QuadCS mode
-            }
-
             if ( l_dimm_type_u8 == fapi2::ENUM_ATTR_CEN_EFF_DIMM_TYPE_RDIMM  )
             {
-                FAPI_TRY(l_data_buffer_8.setBit(1));
+                FAPI_TRY(l_data_buffer_8.setBit(1)); //DUALCS MODE
             }
 
             if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 )
@@ -716,17 +715,6 @@ fapi2::ReturnCode mss_create_rcd_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA
             // RCAx QxODT[1:0] Read Pattern CW
             l_rcd_cntl_word_Ax[l_port][l_dimm] = 0;
 
-            // RCBx IBT and MRS Snoop CW
-            if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 )
-            {
-                l_rcd_cntl_word_Bx[l_port][l_dimm] = 4;
-            }
-            else
-            {
-                l_rcd_cntl_word_Bx[l_port][l_dimm] = 7;
-            }
-
-
             FAPI_TRY(l_data_buffer_64.insertFromRight(l_rcd_cntl_word_1x[l_port][l_dimm], 0 , 8));
             FAPI_TRY(l_data_buffer_64.insertFromRight(l_rcd_cntl_word_2x[l_port][l_dimm], 8 , 8));
             FAPI_TRY(l_data_buffer_64.insertFromRight(l_rcd_cntl_word_3x[l_port][l_dimm], 16, 8));
@@ -768,6 +756,7 @@ fapi2::ReturnCode mss_rcd_load_ddr4(
     uint32_t& io_ccs_inst_cnt
 )
 {
+    uint8_t l_dram_stack[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT];
     uint32_t l_dimm_number = 0;
     uint32_t l_rcd_number = 0;
     fapi2::variable_buffer l_rcd_cntl_wrd_4(8);
@@ -816,11 +805,9 @@ fapi2::ReturnCode mss_rcd_load_ddr4(
     FAPI_TRY(l_odt_4.clearBit(0, 4));
 
 
-
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target, l_dram_stack));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DIMM_TYPE, i_target, l_dimm_type));
-
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_RANKS_PER_DIMM, i_target, l_num_ranks_array));
-
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DIMM_RCD_CNTL_WORD_0_15, i_target, l_rcd_array));
 
 
@@ -885,6 +872,14 @@ fapi2::ReturnCode mss_rcd_load_ddr4(
             FAPI_TRY(l_csn_8.setBit(0, 8), "mss_rcd_load: Error setting up buffers");
             FAPI_TRY(l_csn_8.clearBit(0), "mss_rcd_load: Error setting up buffers"); //DCS0_n is LOW
 
+            if (l_dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
+            {
+                FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!! =====================\n");
+                FAPI_TRY(l_csn_8.clearBit(2, 2));
+                FAPI_TRY(l_csn_8.clearBit(6, 2));
+                FAPI_TRY(l_cke_4.clearBit(1));
+            }
+
             // DBG1, DBG0, DBA1, DBA0 = 4`b0111
             FAPI_TRY(l_bank_3.setBit(0, 3), "mss_rcd_load: Error setting up buffers");
             // DACT_n is HIGH
@@ -1229,7 +1224,7 @@ fapi2::ReturnCode mss_mrs_load_ddr4(
         FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!! =====================\n");
         FAPI_TRY(l_csn_8.clearBit(2, 2));
         FAPI_TRY(l_csn_8.clearBit(6, 2));
-        // COMMENT IN LATER!!!! FAPI_TRY(cke_4.clearBit(1);
+        FAPI_TRY(l_cke_4.clearBit(1));
     }
 
     //MRS0
@@ -2090,8 +2085,8 @@ fapi2::ReturnCode mss_mrs_load_ddr4(
                 if (l_dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
                 {
                     FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!=====================\n");
-                    FAPI_TRY(l_csn_8.clearBit(2 + 4 * l_dimm_number, 2));
-                    // COMMENT IN LATER!!!! FAPI_TRY(l_cke_4.clearBit(1);
+                    FAPI_TRY(l_csn_8.clearBit(2, 2)); // Clearing CKE caused issues here.
+                    FAPI_TRY(l_csn_8.clearBit(6, 2));
                 }
 
                 // Propogate through the 4 MRS cmds
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.C
index 7b460f3c1..bd3ff1e1d 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.C
@@ -969,6 +969,7 @@ fapi2::ReturnCode mss_execute_zq_cal(
         if(l_stack_type[i_port][l_dimm] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
         {
             l_rank_end = l_num_master_ranks_array[i_port][l_dimm];
+
         }
         else
         {
@@ -980,6 +981,14 @@ fapi2::ReturnCode mss_execute_zq_cal(
             FAPI_INF( "+++++++++++++++ Sending zqcal to port: %d rank: %d +++++++++++++++", i_port, l_current_rank);
             l_csn_buffer_8.flush<1>();
             FAPI_TRY(l_csn_buffer_8.clearBit(l_current_rank));
+
+            if(l_stack_type[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
+            {
+                FAPI_TRY(l_csn_buffer_8.clearBit(2, 2));
+                FAPI_TRY(l_csn_buffer_8.clearBit(6, 2));
+                FAPI_TRY(l_cke_buffer_4.clearBit(1));
+            }
+
             //Issue execute.
             FAPI_INF( "+++++++++++++++ Execute CCS array on port: %d +++++++++++++++", i_port);
             FAPI_TRY(mss_ccs_inst_arry_0(i_target, l_instruction_number, l_address_buffer_16, l_bank_buffer_3, l_activate_buffer_1,
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C
index 7ce1ada44..3e78c6282 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C
@@ -118,6 +118,8 @@ extern "C"
         FAPI_INF("\n Running NO -OP command");
         fapi2::buffer<uint8_t> l_data_8;
         fapi2::buffer<uint16_t> l_data_16;
+        uint8_t l_dram_stack[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0};
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target_mba, l_dram_stack));
         //CCS Array 0 Setup
 
         //Buffer conversions from inputs
@@ -131,6 +133,14 @@ extern "C"
         l_csn_8.flush<1>();
         FAPI_TRY(l_csn_8.clearBit(i_rank), "add_activate_to_ccs: Error setting up buffers");
 
+        if (l_dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
+        {
+            FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!=====================\n");
+            FAPI_TRY(l_csn_8.clearBit(2, 2));
+            FAPI_TRY(l_csn_8.clearBit(6, 2));
+            FAPI_TRY(l_cke_4.clearBit(1));
+        }
+
         //Command structure setup
         l_cke_4.flush<1>();
         FAPI_TRY(l_rasn_1.setBit(0), "add_activate_to_ccs: Error setting up buffers");
@@ -389,9 +399,9 @@ extern "C"
                     if (l_dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS)
                     {
                         FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!=====================\n");
-                        FAPI_TRY(l_csn_8.clearBit(2 + 4 * l_dimm_number, 2));
-                        // I'm leaving this commented out - I need to double check it with Luke Mulkey to see which CS's are wired to which CKE's
-                        // FAPI_TRY(l_cke_4.clearBit(1);
+                        FAPI_TRY(l_csn_8.clearBit(2, 2));
+                        FAPI_TRY(l_csn_8.clearBit(6, 2));
+                        FAPI_TRY(l_cke_4.clearBit(1));
                     }
 
                     // Propogate through the 4 MRS cmds
@@ -439,8 +449,6 @@ extern "C"
                              || l_dimm_type == fapi2::ENUM_ATTR_CEN_EFF_DIMM_TYPE_LRDIMM) )
                     {
                         FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n");
-
-
                         // Propogate through the 4 MRS cmds
                         // Copying the current MRS into address buffer matching the MRS_array order
                         // Setting the bank address