diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2019-06-10 09:01:40 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-18 12:59:04 -0500 |
| commit | feab766b57dbfda43ab026a0a04ee80b02d26a18 (patch) | |
| tree | b5ff96f3d84c563af1a2a15ea1bbe6e18d017d17 /src/import/chips/p9 | |
| parent | 450f70a3b34e0e8159df7175fa0f0a1eabb915f8 (diff) | |
| download | talos-hostboot-feab766b57dbfda43ab026a0a04ee80b02d26a18.tar.gz talos-hostboot-feab766b57dbfda43ab026a0a04ee80b02d26a18.zip | |
update i2c bit rate divisor for p9a
p9a i2cm HW changes require nest/4/2/4 programming
Change-Id: Ib29c307fa2250f5096578809e3d0cb10a027086e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78640
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78665
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C | 10 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 17 |
2 files changed, 25 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C index 64153812f..fa51f80f9 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,6 +55,7 @@ fapi2::ReturnCode p9_sbe_i2c_bit_rate_divisor_setting( { uint8_t l_attr_nest_pll_bucket = 0; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2_Type l_i2cm_internal_clk_div2 = 0; fapi2::buffer<uint16_t> l_mb_bit_rate_divisor; fapi2::buffer<uint64_t> l_data64; fapi2::buffer<uint32_t> l_data32; @@ -63,7 +64,12 @@ fapi2::ReturnCode p9_sbe_i2c_bit_rate_divisor_setting( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_attr_nest_pll_bucket)); FAPI_INF("ATTR_NEST_PLL_BUCKET value: %d", l_attr_nest_pll_bucket); - l_mb_bit_rate_divisor = NEST_PLL_FREQ_I2CDIV_LIST[l_attr_nest_pll_bucket - 1]; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2, i_target_chip, l_i2cm_internal_clk_div2)); + + l_mb_bit_rate_divisor = NEST_PLL_FREQ_I2CDIV_LIST[l_attr_nest_pll_bucket - 1] * + ((l_i2cm_internal_clk_div2) ? (2) : (1)); + FAPI_INF("Bit_rate_divisor value: %d", l_mb_bit_rate_divisor); FAPI_DBG("Adjust I2C bit rate divisor setting in I2CM B Mode Reg"); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 9d1b22e69..b5756412b 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -133,6 +133,23 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + I2CM internal clock divider is div2 , not div4 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_DD1_FBC_AND_ALINK</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> |
