support chip swap in memory map via FBC XOR mask programming

p9_sbe_fabricinit.C
p9.fbc.ab_hp.scom.initfile
  set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC
  group/chip ID attribute values, prior to island mode FBC init

  cleanup register/field constant todos

p9_fbc_utils.C
  parametrize p9_fbc_utils_get_chip_base_address to support calculation of
  origin address based on:
    - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS)
    - effective FBC drawer origin -- effective FBC group ID + chip ID=0
      (EFF_FBC_GRP_ID_ONLY)
    - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS)

p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY
  configures BAR address based on drawer base + HRMOR

p9_sbe_load_bootloader.C
  set p9_fbc_utils_get_chip_base_address call for bootloader load to use
  EFF_FBC_GRP_ID_ONLY (drawer)

  store XSCOM/LPC BAR into bootloader config data structure in exception vector
  (based on chip offset)

p9_mss_eff_grouping.C (MCS/HTM BARs)
p9_pcie_config.C (PCIE MMIO BARs)
p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR)
p9_sbe_scominit.C (XSCOM/LPC BARs)
p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox

p9_xip_customize.C
  init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image

Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37777
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

11 files changed, 73 insertions, 26 deletions

diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
index 1004a5e62..f8c9c2554 100644
--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
@@ -148,6 +148,8 @@ fapi2::ReturnCode writeMboxRegs (
     MBOX_ATTR_CLEAR (ATTR_PROC_FABRIC_GROUP_ID,     i_procTarget,   i_image);
     MBOX_ATTR_CLEAR (ATTR_PROC_FABRIC_CHIP_ID,      i_procTarget,   i_image);
     MBOX_ATTR_WRITE (ATTR_DD1_SLOW_PCI_REF_CLOCK,   FAPI_SYSTEM,    i_image);
+    MBOX_ATTR_CLEAR (ATTR_PROC_EFF_FABRIC_GROUP_ID, i_procTarget,   i_image);
+    MBOX_ATTR_CLEAR (ATTR_PROC_EFF_FABRIC_CHIP_ID,  i_procTarget,   i_image);
 
 fapi_try_exit:
     FAPI_DBG("writeMboxRegs Exiting...");
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C
index b22373707..c6203a92b 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C
@@ -33,7 +33,6 @@ constexpr uint64_t literal_0 = 0;
 constexpr uint64_t literal_1 = 1;
 constexpr uint64_t literal_2 = 2;
 constexpr uint64_t literal_3 = 3;
-constexpr uint64_t literal_0b0000000 = 0b0000000;
 constexpr uint64_t literal_4 = 4;
 constexpr uint64_t literal_5 = 5;
 constexpr uint64_t literal_6 = 6;
@@ -239,8 +238,6 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
                 l_scom_buffer.insert<38, 2, 58, uint64_t>(l_PB_COM_PB_CFG_OPT3_MODE_NEXT_NV );
             }
 
-            l_scom_buffer.insert<40, 7, 57, uint64_t>(literal_0b0000000 );
-
             if ((l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_0] == fapi2::ENUM_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG_TRUE))
             {
                 constexpr auto l_PB_COM_PB_CFG_LINK_A0_EN_NEXT_ON = 0x7;
@@ -1264,8 +1261,6 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
                 l_scom_buffer.insert<38, 2, 60, uint64_t>(l_PB_COM_PB_CFG_OPT3_MODE_NEXT_NV );
             }
 
-            l_scom_buffer.insert<40, 7, 57, uint64_t>(literal_0b0000000 );
-
             if ((l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_0] == fapi2::ENUM_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG_TRUE))
             {
                 constexpr auto l_PB_COM_PB_CFG_LINK_A0_EN_NEXT_ON = 0x7;
@@ -2289,8 +2284,6 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
                 l_scom_buffer.insert<38, 2, 62, uint64_t>(l_PB_COM_PB_CFG_OPT3_MODE_NEXT_NV );
             }
 
-            l_scom_buffer.insert<40, 7, 57, uint64_t>(literal_0b0000000 );
-
             if ((l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_0] == fapi2::ENUM_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG_TRUE))
             {
                 constexpr auto l_PB_COM_PB_CFG_LINK_A0_EN_NEXT_ON = 0x7;
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
index ace59a89c..af4df9488 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
@@ -142,14 +142,15 @@ fapi_try_exit:
 
 fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
     uint64_t& o_base_address_nm1,
     uint64_t& o_base_address_m,
     uint64_t& o_base_address_mmio)
 {
-    uint32_t l_fabric_system_id;
-    uint8_t l_fabric_group_id;
-    uint8_t l_fabric_chip_id;
+    uint32_t l_fabric_system_id = 0;
+    uint8_t l_fabric_group_id = 0;
+    uint8_t l_fabric_chip_id = 0;
     uint8_t l_mirror_policy;
     fapi2::buffer<uint64_t> l_base_address;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
@@ -157,19 +158,35 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
 
     FAPI_DBG("Start");
 
-    // retreive attributes which statically determine chip's position in memory map
+    // retreive attributes which statically determine chips position in memory map
+    // use effective group/chip ID attributes to program position specific address bits
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fabric_system_id),
              "Error from FAPI_ATTR_GET (ATTR_FABRIC_SYSTEM_ID)");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
-             "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
-             "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)");
+
+    if (i_addr_mode == ABS_FBC_GRP_CHIP_IDS)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)");
+    }
+    else
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_GROUP_ID)");
+
+        if (i_addr_mode == EFF_FBC_GRP_CHIP_IDS)
+        {
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
+                     "Error from FAPI_ATTR_GET (ATTR_EFF_FABRIC_CHIP_ID)");
+        }
+    }
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy),
              "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)");
 
     // apply system ID
-    // occupies one field for large system map, split into three fields for small system map
+    // occupies one field for large system map (three fields for small system map)
     l_base_address.insertFromRight < FABRIC_ADDR_LS_SYSTEM_ID_START_BIT,
                                    (FABRIC_ADDR_LS_SYSTEM_ID_END_BIT - FABRIC_ADDR_LS_SYSTEM_ID_START_BIT + 1) > (l_fabric_system_id);
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
index f0b30aa1e..23d1df7e9 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -47,6 +47,17 @@
 #include <fapi2.H>
 
 //------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+enum p9_fbc_utils_addr_mode_t
+{
+    EFF_FBC_GRP_CHIP_IDS,  // effective FBC group/chip ID attributes
+    EFF_FBC_GRP_ID_ONLY,   // effective FBC group ID attribute (chip ID=0)
+    ABS_FBC_GRP_CHIP_IDS   // absolute FBC group/chip ID attributes
+};
+
+//------------------------------------------------------------------------------
 // Constant definitions
 //------------------------------------------------------------------------------
 
@@ -91,6 +102,7 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
 /// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip
 ///
 /// @param[in] i_target Reference to processor chip target
+/// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations
 /// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip
 /// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip
 /// @param[out] o_base_address_m Mirrored base address for this chip
@@ -99,10 +111,10 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
 ///
 fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
     uint64_t& o_base_address_nm1,
     uint64_t& o_base_address_m,
     uint64_t& o_base_address_mmio);
 
-
 #endif // _P9_FBC_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
index e39a07995..8a77bde42 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
@@ -213,6 +213,7 @@ fapi2::ReturnCode EffGroupingProcAttrs::calcProcBaseAddr(
 
     // Get the Mirror/Non-mirror base addresses
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+             EFF_FBC_GRP_CHIP_IDS,
              iv_memBaseAddr,
              l_memBaseAddr1,
              iv_mirrorBaseAddr,
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
index 46884e1db..79677fb2c 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
@@ -95,6 +95,7 @@ fapi2::ReturnCode p9_pcie_config(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHI
 
     // determine base address of chip MMIO range
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+             EFF_FBC_GRP_CHIP_IDS,
              l_base_addr_nm0,
              l_base_addr_nm1,
              l_base_addr_m,
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C
index 056edadc9..cbf075979 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C
@@ -113,6 +113,7 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, i_target, l_nx_rng_bar_enable),
              "Error from FAPI_ATTR_GET (ATTR_PROC_NX_BAR_ENABLE)");
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+             EFF_FBC_GRP_CHIP_IDS,
              l_base_addr_nm0,
              l_base_addr_nm1,
              l_base_addr_m,
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
index 4c26ac051..bb2020815 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
@@ -55,18 +55,21 @@ enum SbeBootloaderVersion
     // Keep initial version formatted as it was originally
     INIT = 0x901,
     // Later versions use format [release:2][version:2]
-    SAB_ADDED = 0x00090002
+    SAB_ADDED = 0x00090002,
+    MMIO_BARS_ADDED = 0x00090003,
 };
 
 // Structure starts at the bootloader zero address
 struct BootloaderConfigData_t
 {
-    uint32_t version;  // Some kind of version field so we know if there is new data being added
-    uint8_t sbeBootSide;  // 0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
-    uint8_t pnorBootSide;  // 0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
-    uint16_t pnorSizeMB;  // Size of PNOR in MB  [ATTR_PNOR_SIZE]
-    uint64_t blLoadSize;  // Size of Load (Exception vectors and Bootloader)
-    uint8_t secureAccessBit;
+    uint32_t version;         // bytes  4:7  Version field so we know if there is new data being added
+    uint8_t sbeBootSide;      // byte   8    0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
+    uint8_t pnorBootSide;     // byte   9    0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
+    uint16_t pnorSizeMB;      // bytes 10:11 Size of PNOR in MB  [ATTR_PNOR_SIZE]
+    uint64_t blLoadSize;      // bytes 12:19 Size of Load (Exception vectors and Bootloader)
+    uint8_t secureAccessBit;  // byte  20
+    uint64_t xscomBAR;        // bytes 21:28 XSCOM MMIO BAR
+    uint64_t lpcBAR;          // bytes 29:36 LPC MMIO BAR
 };
 
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
index fb47010a1..513638f6a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
@@ -70,6 +70,7 @@ p9_setup_bars_build_chip_info(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
     FAPI_DBG("Start");
 
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+             EFF_FBC_GRP_CHIP_IDS,
              io_chip_info.base_address_nm[0],
              io_chip_info.base_address_nm[1],
              io_chip_info.base_address_m,
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index 465768d54..62259674c 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -86,11 +86,15 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_SLOW_PCI_REF_CLOCK_BIT        = 5,
 
     // Scratch_reg_6
+    ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT = 17,
+    ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH = 3,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT = 20,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH = 3,
+    ATTR_PUMP_CHIP_IS_GROUP            = 23,
     ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
     ATTR_PROC_FABRIC_GROUP_ID_LENGTH   = 3,
     ATTR_PROC_FABRIC_CHIP_ID_STARTBIT  = 29,
     ATTR_PROC_FABRIC_CHIP_ID_LENGTH    = 3,
-    ATTR_PUMP_CHIP_IS_GROUP            = 23,
 };
 
 
@@ -412,6 +416,17 @@ fapi2::ReturnCode p9_setup_sbe_config(const
         l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_FABRIC_GROUP_ID_LENGTH >(l_read_1);
         l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_FABRIC_CHIP_ID_LENGTH >(l_read_2);
 
+        FAPI_DBG("Reading ATTR_PROC_EFF_FABRIC_GROUP and CHIP_ID");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target_chip,
+                               l_read_1));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip,
+                               l_read_2));
+
+        l_read_scratch_reg.insertFromRight< ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH >
+        (l_read_1);
+        l_read_scratch_reg.insertFromRight< ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH >
+        (l_read_2);
+
         FAPI_DBG("Setting up value of Scratch_reg6");
         //Setting SCRATCH_REGISTER_6 register value
         //CFAM.SCRATCH_REGISTER_6 = l_read_scratch_reg
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index a71c1ffd9..bca8849c6 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -3160,6 +3160,7 @@ fapi2::ReturnCode populateNcuRingBarScomReg( void* i_pChipHomer, CONST_FAPI2_PRO
                  "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET");
 
         FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_procTgt,
+                 EFF_FBC_GRP_CHIP_IDS,
                  baseAddressNm0,
                  baseAddressNm1,
                  baseAddressMirror,