PM: Clear error injection bits before special wake-up in PM complex reset

- Explicitly clear the Hcode error injection bits for SGPE, PGPE and all CMEs
  prior to special wake-up in p9_pm_reset as these will guarentee special
  wake-up failure cause if left set.

Key_Cronus_Test=PM_REGRESS

Change-Id: I618e15633fbce914679a8969901b20d8c5f9b39c
CQ: SW432090
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60062
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60063
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Disable-CI: Christian R. Geddes <crgeddes@us.ibm.com>

2 files changed, 70 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
index cbe5e4c24..1efb4b961 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
@@ -72,7 +72,11 @@
 // -----------------------------------------------------------------------------
 // Constant definitions
 // -----------------------------------------------------------------------------
-
+// Map the auto generated names to clearer ones
+static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR  = PU_OCB_OCI_OCCFLG_SCOM1;
+static const uint64_t PU_OCB_OCI_OCCFLG_SET    = PU_OCB_OCI_OCCFLG_SCOM2;
+static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1;
+static const uint64_t PU_OCB_OCI_OCCFLG2_SET   = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2;
 // -----------------------------------------------------------------------------
 // Global variables
 // -----------------------------------------------------------------------------
@@ -174,6 +178,9 @@ fapi2::ReturnCode p9_pm_reset(
     {
         if (l_malfAlert == false)
         {
+            // Clear the hcode error injection bits so special wake-up can succeed
+            FAPI_TRY(p9_pm_reset_clear_errinj(i_target));
+
             //  ************************************************************************
             //  Put all EX chiplets in special wakeup
             //  ************************************************************************
@@ -727,3 +734,54 @@ fapi_try_exit:
                i_plat, l_phase, l_ffdcEnable );
     return fapi2::current_err;
 }
+
+// Clear all error injection bits of so that the reset state can succeed.
+
+fapi2::ReturnCode p9_pm_reset_clear_errinj (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    fapi2::ATTR_CHIP_UNIT_POS_Type l_chpltNumber = 0;
+
+    FAPI_INF(">> p9_pm_reset_clear_errinj");
+
+    auto l_coreChiplets =
+        i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+        (fapi2::TARGET_STATE_FUNCTIONAL);
+
+    FAPI_INF("Clearing SGPE and PGPE Hcode Error Injection bits");
+    // *INDENT-OFF*
+    l_data64.flush<0>()
+        .setBit<p9hcd::OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ>()
+        .setBit<p9hcd::OCCFLG2_PGPE_HCODE_FIT_ERR_INJ>()
+        .setBit<p9hcd::OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ>();
+    // *INDENT-ON*
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64));
+
+    // For each core target, clear CME injection bits
+    for (auto l_core_chplt : l_coreChiplets)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                               l_core_chplt,
+                               l_chpltNumber),
+                 "ERROR: Failed to get the position of the Core %d",
+                 l_chpltNumber);
+
+        FAPI_INF("Clearing CME Hcode Error Injection and other CSAR settings for core %d",
+                 l_chpltNumber);
+        // *INDENT-OFF*
+        l_data64.flush<0>()
+                .setBit<p9hcd::CPPM_CSAR_FIT_HCODE_ERROR_INJECT>()
+                .setBit<p9hcd::CPPM_CSAR_ENABLE_PSTATE_REGISTRATION_INTERLOCK>()
+                .setBit<p9hcd::CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT>()
+                .setBit<p9hcd::CPPM_CSAR_STOP_HCODE_ERROR_INJECT>();
+        // Note:  CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP is NOT
+        //        cleared as this is a persistent, characterization setting
+        // *INDENT-ON*
+        FAPI_TRY(fapi2::putScom(l_core_chplt, C_CPPM_CSAR_CLEAR, l_data64));
+    }
+
+fapi_try_exit:
+    FAPI_INF("<< p9_pm_reset_clear_errinj");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H
index af685127c..db5acc3b4 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H
@@ -119,5 +119,16 @@ extern "C"
         void* i_pHomerImage,
         const uint8_t i_plat );
 }
+//------------------------------------------------------------------------------
+///
+/// @brief Clear the Hcode error injection bits so special wake-up can succeed
+///
+/// @param[in] i_target Proc Chip target
+///
+/// @return FAPI2_RC_SUCCESS on success, else error code.
+///
+
+fapi2::ReturnCode p9_pm_reset_clear_errinj (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
 
 #endif // _P9_PM_RESET_H