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authorJoe McGill <jmcgill@us.ibm.com>2018-06-15 13:55:15 -0500
committerNicholas E. Bofferding <bofferdn@us.ibm.com>2018-06-20 00:56:29 -0400
commited7254aed9caeb0dddb49de92b8f161c2d4227dc (patch)
treefcabe935c8e56044f079a9691732cc6a0f702e70 /src/import/chips/p9
parent7617e77949d78f00bc575c82de6f2420476a5635 (diff)
downloadtalos-hostboot-ed7254aed9caeb0dddb49de92b8f161c2d4227dc.tar.gz
talos-hostboot-ed7254aed9caeb0dddb49de92b8f161c2d4227dc.zip
use putscomUnderMask API to update FBC DL control register
required to pass SBE FIFO greylist enforcing range update checking Change-Id: I86b300cef571ef47e7db008e4a106ff3b663da39 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60725 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60744 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r--src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C16
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C78
2 files changed, 59 insertions, 35 deletions
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C
index bb15eaf01..49f68e57e 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_linktrain.C
@@ -79,6 +79,8 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
char l_tgt_str[fapi2::MAX_ECMD_STRING_LEN];
fapi2::toString(i_tgt, l_tgt_str, fapi2::MAX_ECMD_STRING_LEN);
fapi2::buffer<uint64_t> l_data = 0;
+ fapi2::buffer<uint64_t> l_dl_control_data;
+ fapi2::buffer<uint64_t> l_dl_control_mask;
fapi2::ATTR_PROC_FABRIC_LINK_ACTIVE_Type l_fbc_active;
fapi2::ATTR_LINK_TRAIN_Type l_link_train;
fapi2::ATTR_CHIP_EC_FEATURE_HW419022_Type l_hw419022 = 0;
@@ -178,13 +180,11 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
// DD1.1+ HW Start training sequence
if(!l_hw419022)
{
-
- l_data.flush<0>();
-
// clear TX lane control overrides
if (l_even)
{
- l_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
+ l_dl_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
+ l_dl_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
FAPI_TRY(fapi2::putScom(i_tgt,
OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL,
@@ -194,7 +194,8 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
if (l_odd)
{
- l_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
+ l_dl_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
+ l_dl_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
FAPI_TRY(fapi2::putScom(i_tgt,
OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL,
@@ -203,7 +204,10 @@ fapi2::ReturnCode p9_io_obus_linktrain(const OBUS_TGT& i_tgt)
}
// Start phy training
- FAPI_TRY(fapi2::putScom(i_tgt, OBUS_LL0_IOOL_CONTROL, l_data),
+ FAPI_TRY(fapi2::putScomUnderMask(i_tgt,
+ OBUS_LL0_IOOL_CONTROL,
+ l_dl_control_data,
+ l_dl_control_mask),
"Error writing DLL control register (0x%08X)!",
OBUS_LL0_IOOL_CONTROL);
}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C
index 42f647d60..d3aa2e0e8 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C
@@ -83,7 +83,8 @@ p9_smp_link_layer_train_link_electrical(
const uint8_t i_en)
{
FAPI_DBG("Start");
- fapi2::buffer<uint64_t> l_dll_control;
+ fapi2::buffer<uint64_t> l_dll_control_data;
+ fapi2::buffer<uint64_t> l_dll_control_mask;
bool l_even = (i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE) ||
(i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_EVEN_ONLY);
@@ -91,22 +92,23 @@ p9_smp_link_layer_train_link_electrical(
bool l_odd = (i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_TRUE) ||
(i_en == fapi2::ENUM_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG_ODD_ONLY);
- // read control register
- FAPI_TRY(fapi2::getScom(i_target, i_ctl.dl_control_addr, l_dll_control),
- "Error reading DLL control register (0x%08X)!",
- i_ctl.dl_control_addr);
-
if (l_even)
{
- l_dll_control.setBit<XBUS_LL0_IOEL_CONTROL_LINK0_STARTUP>();
+ l_dll_control_data.setBit<XBUS_LL0_IOEL_CONTROL_LINK0_STARTUP>();
+ l_dll_control_mask.setBit<XBUS_LL0_IOEL_CONTROL_LINK0_STARTUP>();
}
if (l_odd)
{
- l_dll_control.setBit<XBUS_LL0_IOEL_CONTROL_LINK1_STARTUP>();
+ l_dll_control_data.setBit<XBUS_LL0_IOEL_CONTROL_LINK1_STARTUP>();
+ l_dll_control_mask.setBit<XBUS_LL0_IOEL_CONTROL_LINK1_STARTUP>();
}
- FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control),
+ // update control register
+ FAPI_TRY(fapi2::putScomUnderMask(i_target,
+ i_ctl.dl_control_addr,
+ l_dll_control_data,
+ l_dll_control_mask),
"Error writing DLL control register (0x%08X)!",
i_ctl.dl_control_addr);
@@ -266,7 +268,8 @@ p9_smp_link_layer_train_link_optical(
const uint8_t i_en)
{
FAPI_DBG("Start");
- fapi2::buffer<uint64_t> l_dll_control;
+ fapi2::buffer<uint64_t> l_dll_control_data;
+ fapi2::buffer<uint64_t> l_dll_control_mask;
fapi2::Target<fapi2::TARGET_TYPE_OBUS> l_loc_target;
fapi2::Target<fapi2::TARGET_TYPE_OBUS> l_rem_target;
fapi2::ATTR_CHIP_EC_FEATURE_HW419022_Type l_hw419022 = 0;
@@ -301,26 +304,28 @@ p9_smp_link_layer_train_link_optical(
FAPI_TRY(l_loc_target.getOtherEnd(l_rem_target),
"Error from getOtherEnd");
- // read control register
- FAPI_TRY(fapi2::getScom(i_target, i_ctl.dl_control_addr, l_dll_control),
- "Error reading DLL control register (0x%08X)!",
- i_ctl.dl_control_addr);
-
if (!l_hw419022)
{
if (l_even)
{
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
}
if (l_odd)
{
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
}
- FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control),
+ FAPI_TRY(fapi2::putScomUnderMask(i_target,
+ i_ctl.dl_control_addr,
+ l_dll_control_data,
+ l_dll_control_mask),
"Error writing DLL control register (0x%08X)!",
i_ctl.dl_control_addr);
}
@@ -329,15 +334,20 @@ p9_smp_link_layer_train_link_optical(
// force assertion of run_lane
if (l_even)
{
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE>();
}
if (l_odd)
{
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE>();
}
- FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control),
+ FAPI_TRY(fapi2::putScomUnderMask(i_target,
+ i_ctl.dl_control_addr,
+ l_dll_control_data,
+ l_dll_control_mask),
"Error writing DLL control register (0x%08X, force RUN_LANE)",
i_ctl.dl_control_addr);
@@ -365,30 +375,40 @@ p9_smp_link_layer_train_link_optical(
// enable link startup
if (l_even)
{
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP>();
}
if (l_odd)
{
- l_dll_control.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
+ l_dll_control_data.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP>();
}
- FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control),
+ FAPI_TRY(fapi2::putScomUnderMask(i_target,
+ i_ctl.dl_control_addr,
+ l_dll_control_data,
+ l_dll_control_mask),
"Error writing DLL control register (0x%08X, set LINK_STARTUP)!",
i_ctl.dl_control_addr);
// disable run lane override
if (l_even)
{
- l_dll_control.clearBit<OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE>();
+ l_dll_control_data.clearBit<OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE>();
}
if (l_odd)
{
- l_dll_control.clearBit<OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE>();
+ l_dll_control_data.clearBit<OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE>();
+ l_dll_control_mask.setBit<OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE>();
}
- FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control),
+ FAPI_TRY(fapi2::putScomUnderMask(i_target,
+ i_ctl.dl_control_addr,
+ l_dll_control_data,
+ l_dll_control_mask),
"Error writing DLL control register (0x%08X, clar RUN_LANE_OVERRIDE)!",
i_ctl.dl_control_addr);
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