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| author | Chris Yan <fyan@us.ibm.com> | 2016-08-04 15:36:47 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-08-09 14:22:33 -0400 |
| commit | d54c522395bb266a125b4fe1d2a96578f3edd5c4 (patch) | |
| tree | 365ed33b8c09e2f52489f09ab168591455f99c3b /src/import/chips/p9 | |
| parent | c3e0a9ea1d0d43892cce1c507782b72dfec66494 (diff) | |
| download | talos-hostboot-d54c522395bb266a125b4fe1d2a96578f3edd5c4.tar.gz talos-hostboot-d54c522395bb266a125b4fe1d2a96578f3edd5c4.zip | |
Update MR and MT VPD. Add support for Impedance CNTL.
Updated fake vpd
Change-Id: Ibdc07d3cbf517d8bd3f5192218205e3680f7eeb6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27889
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27940
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
5 files changed, 936 insertions, 381 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 501fe42e9..d536d1d15 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -22474,7 +22474,7 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -22483,24 +22483,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -22509,25 +22509,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -22536,7 +22536,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -22547,18 +22547,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2:: uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -22567,24 +22567,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -22593,25 +22593,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -22620,7 +22620,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -22631,18 +22631,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2:: uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -22651,24 +22651,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -22677,25 +22677,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -22704,7 +22704,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -22715,18 +22715,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2:: uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -22735,24 +22735,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -22761,25 +22761,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -22788,7 +22788,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -22799,12 +22799,12 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2:: uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -24382,40 +24382,127 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination in tens of +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + uint8_t l_value[2][2]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2]; + auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, i_target, l_value) ); + memcpy(o_array, &l_value, 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (F) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) { uint8_t l_value[2][2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT, l_mcs, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, l_mcs, l_value) ); o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination in tens of +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -24426,26 +24513,27 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_T uint8_t l_value[2][2]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT, l_mcs, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, l_mcs, l_value) ); memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination in tens of +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -24455,12 +24543,184 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_T uint8_t l_value[2][2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, i_target, l_value) ); memcpy(o_array, &l_value, 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (F) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + uint8_t l_value[2][2]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2]; + auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, i_target, l_value) ); + memcpy(o_array, &l_value, 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (F) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + uint8_t l_value[2][2]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2]; + auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, i_target, l_value) ); + memcpy(o_array, &l_value, 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -24483,12 +24743,12 @@ inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::T return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 2); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -24515,11 +24775,11 @@ inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::T return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -24546,10 +24806,10 @@ inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::T return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -24575,12 +24835,12 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_T return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 2); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -24606,11 +24866,11 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_T return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -24636,10 +24896,10 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_T return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -24665,12 +24925,12 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_ return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 2); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -24696,11 +24956,11 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_ return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -24726,10 +24986,10 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_ return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -24755,12 +25015,12 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TY return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 2); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -24786,11 +25046,11 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TY return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -24816,10 +25076,10 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TY return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -25340,64 +25600,62 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address Lines in +/// @note Memory Controller side Drive Impedance for Clock in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address Lines in +/// @note Memory Controller side Drive Impedance for Clock in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address Lines in +/// @note Memory Controller side Drive Impedance for Clock in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -25407,73 +25665,81 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGE uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and +/// Activate Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and +/// Activate Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and +/// Activate Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -25483,12 +25749,12 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -25499,7 +25765,8 @@ fapi_try_exit: /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Control Lines in +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset +/// Lines in /// Ohms. /// inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) @@ -25523,7 +25790,8 @@ fapi_try_exit: /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Control Lines in +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset +/// Lines in /// Ohms. /// inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, @@ -25548,7 +25816,8 @@ fapi_try_exit: /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Control Lines in +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset +/// Lines in /// Ohms. /// inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) @@ -25572,65 +25841,65 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Data and Data Strobe Lines in +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Data and Data Strobe Lines in +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Data and Data Strobe Lines in +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -25641,76 +25910,86 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TAR uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable Spare Line in +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { - uint8_t l_value[2]; + uint8_t l_value[2][5]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable Spare Line in +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t* o_array) { - uint8_t l_value[2]; - auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + uint8_t l_value[2][5]; + auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 5); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable Spare Line in +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -25719,35 +25998,37 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARG return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2]; + uint8_t l_value[2][5]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 10); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// /// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Impedance for Data and Data Strobe Lines in +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { - uint8_t l_value[2]; + uint8_t l_value[2][5]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: @@ -25758,21 +26039,28 @@ fapi_try_exit: /// /// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Impedance for Data and Data Strobe Lines in +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t* o_array) { - uint8_t l_value[2]; - auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + uint8_t l_value[2][5]; + auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 5); return fapi2::current_err; fapi_try_exit: @@ -25785,9 +26073,10 @@ fapi_try_exit: /// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Impedance for Data and Data Strobe Lines in +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in /// Ohms. /// inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, @@ -25799,10 +26088,10 @@ inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TAR return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2]; + uint8_t l_value[2][5]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + memcpy(o_array, &l_value, 10); return fapi2::current_err; fapi_try_exit: @@ -25828,12 +26117,12 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_DI return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 2); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -25859,11 +26148,11 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MC return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -25889,10 +26178,10 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MC return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -25918,12 +26207,12 @@ inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DI return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 2); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -25949,11 +26238,11 @@ inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MC return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: @@ -25979,10 +26268,10 @@ inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MC return fapi2::FAPI2_RC_INVALID_PARAMETER; } - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: @@ -25992,6 +26281,85 @@ fapi_try_exit: } /// +/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Number of clocks used for preamble. Calibration only uses 1 nCK preamble +/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble +/// option. +/// +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Number of clocks used for preamble. Calibration only uses 1 nCK preamble +/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble +/// option. +/// +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + uint8_t l_value[2]; + auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + o_value = l_value[mss::index(l_mca)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter +/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Number of clocks used for preamble. Calibration only uses 1 nCK preamble +/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble +/// option. +/// +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array) +{ + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MSS_VPD_MT_VREF_DRAM_WR getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint8_t diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H index ede76118a..33afc8692 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H @@ -99,13 +99,13 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT decode and set (array) +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA decode and set (array) /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Register Clock Driver, Input Bus Termination in tens of Ohms. +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of Ohms. /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { uint8_t l_value[2][2]; @@ -120,8 +120,95 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt(const fapi2::Target<fapi2::TARGET_T memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length); } - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT start: 6, len: 4"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA start: 6, len: 4"); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE decode and set (array) +/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + const std::vector<uint8_t*>& i_blobs) +{ + uint8_t l_value[2][2]; + const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); + const uint64_t l_length = 4 / l_mcas.size(); + + for (const auto& l_mca : l_mcas) + { + const uint64_t l_index = mss::index(l_mca); + const uint8_t* l_blob = i_blobs[l_index]; + const uint64_t l_start = 10 + (l_index * l_length); + memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length); + } + + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE start: 10, len: 4"); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS decode and set (array) +/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + const std::vector<uint8_t*>& i_blobs) +{ + uint8_t l_value[2][2]; + const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); + const uint64_t l_length = 4 / l_mcas.size(); + + for (const auto& l_mca : l_mcas) + { + const uint64_t l_index = mss::index(l_mca); + const uint8_t* l_blob = i_blobs[l_index]; + const uint64_t l_start = 14 + (l_index * l_length); + memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length); + } + + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS start: 14, len: 4"); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT decode and set (array) +/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of Ohms. +/// +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + const std::vector<uint8_t*>& i_blobs) +{ + uint8_t l_value[2][2]; + const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); + const uint64_t l_length = 4 / l_mcas.size(); + + for (const auto& l_mca : l_mcas) + { + const uint64_t l_index = mss::index(l_mca); + const uint8_t* l_blob = i_blobs[l_index]; + const uint64_t l_start = 18 + (l_index * l_length); + memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length); + } + + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT start: 18, len: 4"); fapi_try_exit: return fapi2::current_err; @@ -137,20 +224,20 @@ fapi_try_exit: inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 8 / l_mcas.size(); + const uint64_t l_length = 16 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 10 + (l_index * l_length); + const uint64_t l_start = 22 + (l_index * l_length); memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS start: 10, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS start: 22, len: 16"); fapi_try_exit: return fapi2::current_err; @@ -166,20 +253,20 @@ fapi_try_exit: inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 8 / l_mcas.size(); + const uint64_t l_length = 16 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 18 + (l_index * l_length); + const uint64_t l_start = 38 + (l_index * l_length); memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_NOM start: 18, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_NOM start: 38, len: 16"); fapi_try_exit: return fapi2::current_err; @@ -195,20 +282,20 @@ fapi_try_exit: inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 8 / l_mcas.size(); + const uint64_t l_length = 16 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 26 + (l_index * l_length); + const uint64_t l_start = 54 + (l_index * l_length); memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_PARK start: 26, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_PARK start: 54, len: 16"); fapi_try_exit: return fapi2::current_err; @@ -224,20 +311,20 @@ fapi_try_exit: inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 8 / l_mcas.size(); + const uint64_t l_length = 16 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 34 + (l_index * l_length); + const uint64_t l_start = 70 + (l_index * l_length); memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_WR start: 34, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_WR start: 70, len: 16"); fapi_try_exit: return fapi2::current_err; @@ -271,7 +358,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::T { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 42 + (l_index * l_length); + const uint64_t l_start = 86 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -281,7 +368,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::T } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP start: 42, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP start: 86, len: 8"); fapi_try_exit: return fapi2::current_err; @@ -315,7 +402,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2: { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 50 + (l_index * l_length); + const uint64_t l_start = 94 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -325,7 +412,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2: } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN start: 50, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN start: 94, len: 8"); fapi_try_exit: return fapi2::current_err; @@ -359,7 +446,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::T { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 58 + (l_index * l_length); + const uint64_t l_start = 102 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -369,7 +456,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::T } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP start: 58, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP start: 102, len: 8"); fapi_try_exit: return fapi2::current_err; @@ -401,7 +488,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 66 + (l_index * l_length); + const uint64_t l_start = 110 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -411,7 +498,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP start: 66, len: 16"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP start: 110, len: 16"); fapi_try_exit: return fapi2::current_err; @@ -443,7 +530,7 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 82 + (l_index * l_length); + const uint64_t l_start = 126 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -453,20 +540,20 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES start: 82, len: 16"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES start: 126, len: 16"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR decode and set (array) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK decode and set (array) /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Memory Controller side Drive Impedance for Address Lines in Ohms. +/// @note Memory Controller side Drive Impedance for Clock in Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { uint8_t l_value[2]; @@ -477,25 +564,25 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_addr(const fapi2::Target<fapi2::TARGE { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 98 + (l_index * l_length); + const uint64_t l_start = 142 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR start: 98, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK start: 142, len: 2"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK decode and set (array) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR decode and set (array) /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Memory Controller side Drive Impedance for Clock in Ohms. +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { uint8_t l_value[2]; @@ -506,12 +593,12 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 100 + (l_index * l_length); + const uint64_t l_start = 144 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK start: 100, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR start: 144, len: 2"); fapi_try_exit: return fapi2::current_err; @@ -522,7 +609,7 @@ fapi_try_exit: /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Memory Controller side Drive Impedance for Control Lines in Ohms. +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. /// inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) @@ -535,25 +622,25 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGE { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 102 + (l_index * l_length); + const uint64_t l_start = 146 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL start: 102, len: 2"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL start: 146, len: 2"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS decode and set (array) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID decode and set (array) /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Memory Controller side Drive Impedance for Data and Data Strobe Lines in Ohms. +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { uint8_t l_value[2]; @@ -564,41 +651,41 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TAR { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 104 + (l_index * l_length); + const uint64_t l_start = 148 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS start: 104, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID start: 148, len: 2"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE decode and set (array) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS decode and set (array) /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Memory Controller side Drive Impedance for Clock Enable Spare Line in Ohms. +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe Lines in Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_spcke(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2]; + uint8_t l_value[2][5]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 2 / l_mcas.size(); + const uint64_t l_length = 10 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 106 + (l_index * l_length); - memcpy(&(l_value[l_index]), l_blob + l_start, l_length); + const uint64_t l_start = 150 + (l_index * l_length); + memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length); } - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE start: 106, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS start: 150, len: 10"); fapi_try_exit: return fapi2::current_err; @@ -609,25 +696,25 @@ fapi_try_exit: /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK -/// @note Memory Controller side Receiver Impedance for Data and Data Strobe Lines in Ohms. +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2]; + uint8_t l_value[2][5]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 2 / l_mcas.size(); + const uint64_t l_length = 10 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 108 + (l_index * l_length); - memcpy(&(l_value[l_index]), l_blob + l_start, l_length); + const uint64_t l_start = 160 + (l_index * l_length); + memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS start: 108, len: 2"); + "Unable to decode and set ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS start: 160, len: 10"); fapi_try_exit: return fapi2::current_err; @@ -643,20 +730,20 @@ fapi_try_exit: inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 8 / l_mcas.size(); + const uint64_t l_length = 16 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 110 + (l_index * l_length); + const uint64_t l_start = 170 + (l_index * l_length); memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_ODT_RD start: 110, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_ODT_RD start: 170, len: 16"); fapi_try_exit: return fapi2::current_err; @@ -672,20 +759,49 @@ fapi_try_exit: inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const std::vector<uint8_t*>& i_blobs) { - uint8_t l_value[2][2][2]; + uint8_t l_value[2][2][4]; const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const uint64_t l_length = 8 / l_mcas.size(); + const uint64_t l_length = 16 / l_mcas.size(); for (const auto& l_mca : l_mcas) { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 118 + (l_index * l_length); + const uint64_t l_start = 186 + (l_index * l_length); memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_ODT_WR start: 118, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_ODT_WR start: 186, len: 16"); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_PREAMBLE decode and set (array) +/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> +/// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Number of clocks used for preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. +/// +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + const std::vector<uint8_t*>& i_blobs) +{ + uint8_t l_value[2]; + const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); + const uint64_t l_length = 2 / l_mcas.size(); + + for (const auto& l_mca : l_mcas) + { + const uint64_t l_index = mss::index(l_mca); + const uint8_t* l_blob = i_blobs[l_index]; + const uint64_t l_start = 202 + (l_index * l_length); + memcpy(&(l_value[l_index]), l_blob + l_start, l_length); + } + + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MT_PREAMBLE start: 202, len: 2"); fapi_try_exit: return fapi2::current_err; @@ -709,12 +825,12 @@ inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_T { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 126 + (l_index * l_length); + const uint64_t l_start = 204 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_VREF_DRAM_WR start: 126, len: 2"); + "Unable to decode and set ATTR_MSS_VPD_MT_VREF_DRAM_WR start: 204, len: 2"); fapi_try_exit: return fapi2::current_err; @@ -738,7 +854,7 @@ inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYP { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 128 + (l_index * l_length); + const uint64_t l_start = 206 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -748,7 +864,7 @@ inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYP } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_VREF_MC_RD start: 128, len: 8"); + "Unable to decode and set ATTR_MSS_VPD_MT_VREF_MC_RD start: 206, len: 8"); fapi_try_exit: return fapi2::current_err; @@ -772,7 +888,7 @@ inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET { const uint64_t l_index = mss::index(l_mca); const uint8_t* l_blob = i_blobs[l_index]; - const uint64_t l_start = 136 + (l_index * l_length); + const uint64_t l_start = 214 + (l_index * l_length); memcpy(&(l_value[l_index]), l_blob + l_start, l_length); } @@ -782,7 +898,7 @@ inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MT_WINDAGE_RD_CTR start: 136, len: 4"); + "Unable to decode and set ATTR_MSS_VPD_MT_WINDAGE_RD_CTR start: 214, len: 4"); fapi_try_exit: return fapi2::current_err; @@ -1292,80 +1408,80 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0 decode and set +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP decode and set /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blob the VPD blob for this MCS /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK /// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob) { uint8_t l_value[2]; memcpy(&l_value, i_blob + 50, 2); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0 start: 50, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP start: 50, len: 2"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1 decode and set +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN decode and set /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blob the VPD blob for this MCS /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK /// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob) { uint8_t l_value[2]; memcpy(&l_value, i_blob + 52, 2); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1 start: 52, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN start: 52, len: 2"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0 decode and set +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP decode and set /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blob the VPD blob for this MCS /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK /// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob) { uint8_t l_value[2]; memcpy(&l_value, i_blob + 54, 2); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0 start: 54, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP start: 54, len: 2"); fapi_try_exit: return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1 decode and set +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN decode and set /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS> /// @param[in] i_blob the VPD blob for this MCS /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK /// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clk1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob) { uint8_t l_value[2]; memcpy(&l_value, i_blob + 56, 2); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1, i_target, l_value), - "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1 start: 56, len: 2"); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value), + "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN start: 56, len: 2"); fapi_try_exit: return fapi2::current_err; @@ -1747,7 +1863,10 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& FAPI_TRY (decoder::vpd_mt_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) ); - FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_ca(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_cke(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_cs(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_odt(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_dram_drv_imp_dq_dqs(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_dram_rtt_nom(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_dram_rtt_park(i_target, i_mt_blob) ); @@ -1757,14 +1876,15 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_wr_up(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_mc_dq_ctle_cap(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_mc_dq_ctle_res(i_target, i_mt_blob) ); - FAPI_TRY (decoder::vpd_mt_mc_drv_imp_addr(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_mc_drv_imp_clk(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_mc_drv_imp_cmd_addr(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_mc_drv_imp_cntl(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_mc_drv_imp_cscid(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_mc_drv_imp_dq_dqs(i_target, i_mt_blob) ); - FAPI_TRY (decoder::vpd_mt_mc_drv_imp_spcke(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_mc_rcv_imp_dq_dqs(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_odt_rd(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_odt_wr(i_target, i_mt_blob) ); + FAPI_TRY (decoder::vpd_mt_preamble(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_vref_dram_wr(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_vref_mc_rd(i_target, i_mt_blob) ); FAPI_TRY (decoder::vpd_mt_windage_rd_ctr(i_target, i_mt_blob) ); @@ -1793,10 +1913,10 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c0(i_target, i_mr_blob) ); FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c1(i_target, i_mr_blob) ); FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c2(i_target, i_mr_blob) ); - FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clk0(i_target, i_mr_blob) ); - FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clk1(i_target, i_mr_blob) ); - FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clk0(i_target, i_mr_blob) ); - FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clk1(i_target, i_mr_blob) ); + FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clkp(i_target, i_mr_blob) ); + FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clkn(i_target, i_mr_blob) ); + FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clkp(i_target, i_mr_blob) ); + FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clkn(i_target, i_mr_blob) ); FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_actn(i_target, i_mr_blob) ); FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_casn_a15(i_target, i_mr_blob) ); FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(i_target, i_mr_blob) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C index 0cd1cab34..dea9d53b3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C @@ -40,24 +40,24 @@ namespace mss { -// VPD data from template_mt and template_mr - shouldbe VBU/sim settings +// VPD data from template_mt and template_mr - should be VBU/sim settings constexpr auto raw_mt_size = 255; static constexpr uint8_t raw_mt[raw_mt_size] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, - 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x22, 0x22, 0x28, 0x28, 0x3c, 0x3c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x16, 0x16, - 0x00, 0x01, 0x31, 0xaa, 0x00, 0x01, 0x31, 0xaa, 0x80, 0x23, 0x80, 0x23, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, + 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, + 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x28, + 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, + 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x16, 0x16, 0x00, 0x01, + 0x31, 0xaa, 0x00, 0x01, 0x31, 0xaa, 0x80, 0x23, 0x80, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml index db6be426b..33cbaae1d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml @@ -421,7 +421,7 @@ </attribute> <attribute> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK0</id> + <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id> <targetType>TARGET_TYPE_MCS</targetType> <description> Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. @@ -432,12 +432,12 @@ <mssUnits>tick</mssUnits> <mssBlobStart>50</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mr_mc_phase_rot_d0_clk0</mssAccessorName> + <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkp</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLK1</id> + <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id> <targetType>TARGET_TYPE_MCS</targetType> <description> Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. @@ -448,12 +448,12 @@ <mssUnits>tick</mssUnits> <mssBlobStart>52</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mr_mc_phase_rot_d0_clk1</mssAccessorName> + <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkn</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK0</id> + <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id> <targetType>TARGET_TYPE_MCS</targetType> <description> Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. @@ -464,12 +464,12 @@ <mssUnits>tick</mssUnits> <mssBlobStart>54</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mr_mc_phase_rot_d1_clk0</mssAccessorName> + <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkp</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLK1</id> + <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id> <targetType>TARGET_TYPE_MCS</targetType> <description> Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock. @@ -480,7 +480,7 @@ <mssUnits>tick</mssUnits> <mssBlobStart>56</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mr_mc_phase_rot_d1_clk1</mssAccessorName> + <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkn</mssAccessorName> <array>2</array> </attribute> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml index 01a1e791c..ef47f5998 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml @@ -69,10 +69,10 @@ </attribute> <attribute> - <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT</id> + <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Register Clock Driver, Input Bus Termination in tens of Ohms. + Register Clock Driver, Input Bus Termination for Command/Address in tens of Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -81,7 +81,58 @@ <mssUnits>ohm</mssUnits> <mssBlobStart>6</mssBlobStart> <mssBlobLength>4</mssBlobLength> - <mssAccessorName>vpd_mt_dimm_rcd_ibt</mssAccessorName> + <mssAccessorName>vpd_mt_dimm_rcd_ibt_ca</mssAccessorName> + <array>2 2</array> + </attribute> + + <attribute> + <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Register Clock Driver, Input Bus Termination for Clock Enable in tens of Ohms. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30</enum> + <mssUnits>ohm</mssUnits> + <mssBlobStart>10</mssBlobStart> + <mssBlobLength>4</mssBlobLength> + <mssAccessorName>vpd_mt_dimm_rcd_ibt_cke</mssAccessorName> + <array>2 2</array> + </attribute> + + <attribute> + <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Register Clock Driver, Input Bus Termination for Chip Select in tens of Ohms. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30</enum> + <mssUnits>ohm</mssUnits> + <mssBlobStart>14</mssBlobStart> + <mssBlobLength>4</mssBlobLength> + <mssAccessorName>vpd_mt_dimm_rcd_ibt_cs</mssAccessorName> + <array>2 2</array> + </attribute> + + <attribute> + <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Register Clock Driver, Input Bus Termination for On Die Termination in tens of Ohms. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30</enum> + <mssUnits>ohm</mssUnits> + <mssBlobStart>18</mssBlobStart> + <mssBlobLength>4</mssBlobLength> + <mssAccessorName>vpd_mt_dimm_rcd_ibt_odt</mssAccessorName> <array>2 2</array> </attribute> @@ -96,10 +147,10 @@ <writeable/> <enum>OHM34 = 34, OHM48 = 48</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>10</mssBlobStart> - <mssBlobLength>8</mssBlobLength> + <mssBlobStart>22</mssBlobStart> + <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_dram_drv_imp_dq_dqs</mssAccessorName> - <array>2 2 2</array> + <array>2 2 4</array> </attribute> <attribute> @@ -113,10 +164,10 @@ <writeable/> <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>18</mssBlobStart> - <mssBlobLength>8</mssBlobLength> + <mssBlobStart>38</mssBlobStart> + <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_dram_rtt_nom</mssAccessorName> - <array>2 2 2</array> + <array>2 2 4</array> </attribute> <attribute> @@ -130,10 +181,10 @@ <writeable/> <enum>DISABLE = 0, 60OHM = 60, 120OHM = 120, 40OHM = 40, 240OHM = 240, 48OHM = 48, 80OHM = 80, 34OHM = 34</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>26</mssBlobStart> - <mssBlobLength>8</mssBlobLength> + <mssBlobStart>54</mssBlobStart> + <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_dram_rtt_park</mssAccessorName> - <array>2 2 2</array> + <array>2 2 4</array> </attribute> <attribute> @@ -147,10 +198,10 @@ <writeable/> <enum>DISABLE = 0, OHM80 = 80, OHM120 = 120, OHM240 = 240, HIGHZ = 1</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>34</mssBlobStart> - <mssBlobLength>8</mssBlobLength> + <mssBlobStart>70</mssBlobStart> + <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_dram_rtt_wr</mssAccessorName> - <array>2 2 2</array> + <array>2 2 4</array> </attribute> <attribute> @@ -173,7 +224,7 @@ <valueType>uint32</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>42</mssBlobStart> + <mssBlobStart>86</mssBlobStart> <mssBlobLength>8</mssBlobLength> <mssAccessorName>vpd_mt_mc_dq_acboost_rd_up</mssAccessorName> <array>2</array> @@ -199,7 +250,7 @@ <valueType>uint32</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>50</mssBlobStart> + <mssBlobStart>94</mssBlobStart> <mssBlobLength>8</mssBlobLength> <mssAccessorName>vpd_mt_mc_dq_acboost_wr_down</mssAccessorName> <array>2</array> @@ -225,7 +276,7 @@ <valueType>uint32</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>58</mssBlobStart> + <mssBlobStart>102</mssBlobStart> <mssBlobLength>8</mssBlobLength> <mssAccessorName>vpd_mt_mc_dq_acboost_wr_up</mssAccessorName> <array>2</array> @@ -249,7 +300,7 @@ <valueType>uint64</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>66</mssBlobStart> + <mssBlobStart>110</mssBlobStart> <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_mc_dq_ctle_cap</mssAccessorName> <array>2</array> @@ -273,43 +324,43 @@ <valueType>uint64</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>82</mssBlobStart> + <mssBlobStart>126</mssBlobStart> <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_mc_dq_ctle_res</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_ADDR</id> + <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Memory Controller side Drive Impedance for Address Lines in Ohms. + Memory Controller side Drive Impedance for Clock in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> <enum>OHM30 = 30, OHM40 = 40</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>98</mssBlobStart> + <mssBlobStart>142</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mt_mc_drv_imp_addr</mssAccessorName> + <mssAccessorName>vpd_mt_mc_drv_imp_clk</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK</id> + <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Memory Controller side Drive Impedance for Clock in Ohms. + Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> <enum>OHM30 = 30, OHM40 = 40</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>100</mssBlobStart> + <mssBlobStart>144</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mt_mc_drv_imp_clk</mssAccessorName> + <mssAccessorName>vpd_mt_mc_drv_imp_cmd_addr</mssAccessorName> <array>2</array> </attribute> @@ -317,68 +368,68 @@ <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Memory Controller side Drive Impedance for Control Lines in Ohms. + Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> <enum>OHM30 = 30, OHM40 = 40</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>102</mssBlobStart> + <mssBlobStart>146</mssBlobStart> <mssBlobLength>2</mssBlobLength> <mssAccessorName>vpd_mt_mc_drv_imp_cntl</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS</id> + <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Memory Controller side Drive Impedance for Data and Data Strobe Lines in Ohms. + Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> + <enum>OHM30 = 30, OHM40 = 40</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>104</mssBlobStart> + <mssBlobStart>148</mssBlobStart> <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mt_mc_drv_imp_dq_dqs</mssAccessorName> + <mssAccessorName>vpd_mt_mc_drv_imp_cscid</mssAccessorName> <array>2</array> </attribute> <attribute> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_SPCKE</id> + <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Memory Controller side Drive Impedance for Clock Enable Spare Line in Ohms. + Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>OHM30 = 30, OHM40 = 40</enum> + <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>106</mssBlobStart> - <mssBlobLength>2</mssBlobLength> - <mssAccessorName>vpd_mt_mc_drv_imp_spcke</mssAccessorName> - <array>2</array> + <mssBlobStart>150</mssBlobStart> + <mssBlobLength>10</mssBlobLength> + <mssAccessorName>vpd_mt_mc_drv_imp_dq_dqs</mssAccessorName> + <array>2 5</array> </attribute> <attribute> <id>ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Memory Controller side Receiver Impedance for Data and Data Strobe Lines in Ohms. + Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>DISABLE = 0, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> + <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum> <mssUnits>ohm</mssUnits> - <mssBlobStart>108</mssBlobStart> - <mssBlobLength>2</mssBlobLength> + <mssBlobStart>160</mssBlobStart> + <mssBlobLength>10</mssBlobLength> <mssAccessorName>vpd_mt_mc_rcv_imp_dq_dqs</mssAccessorName> - <array>2</array> + <array>2 5</array> </attribute> <attribute> @@ -391,10 +442,10 @@ <valueType>uint8</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>110</mssBlobStart> - <mssBlobLength>8</mssBlobLength> + <mssBlobStart>170</mssBlobStart> + <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_odt_rd</mssAccessorName> - <array>2 2 2</array> + <array>2 2 4</array> </attribute> <attribute> @@ -407,10 +458,26 @@ <valueType>uint8</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>118</mssBlobStart> - <mssBlobLength>8</mssBlobLength> + <mssBlobStart>186</mssBlobStart> + <mssBlobLength>16</mssBlobLength> <mssAccessorName>vpd_mt_odt_wr</mssAccessorName> - <array>2 2 2</array> + <array>2 2 4</array> + </attribute> + + <attribute> + <id>ATTR_MSS_VPD_MT_PREAMBLE</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Number of clocks used for preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nCK</mssUnits> + <mssBlobStart>202</mssBlobStart> + <mssBlobLength>2</mssBlobLength> + <mssAccessorName>vpd_mt_preamble</mssAccessorName> + <array>2</array> </attribute> <attribute> @@ -423,7 +490,7 @@ <valueType>uint8</valueType> <writeable/> <mssUnits></mssUnits> - <mssBlobStart>126</mssBlobStart> + <mssBlobStart>204</mssBlobStart> <mssBlobLength>2</mssBlobLength> <mssAccessorName>vpd_mt_vref_dram_wr</mssAccessorName> <array>2</array> @@ -440,7 +507,7 @@ <writeable/> <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum> <mssUnits>percent of Vdd</mssUnits> - <mssBlobStart>128</mssBlobStart> + <mssBlobStart>206</mssBlobStart> <mssBlobLength>8</mssBlobLength> <mssAccessorName>vpd_mt_vref_mc_rd</mssAccessorName> <array>2</array> @@ -456,7 +523,7 @@ <valueType>uint16</valueType> <writeable/> <mssUnits>num</mssUnits> - <mssBlobStart>136</mssBlobStart> + <mssBlobStart>214</mssBlobStart> <mssBlobLength>4</mssBlobLength> <mssAccessorName>vpd_mt_windage_rd_ctr</mssAccessorName> <array>2</array> |
