diff options
author | Yue Du <daviddu@us.ibm.com> | 2016-07-21 14:32:19 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-01 11:46:08 -0400 |
commit | c9c3f24168195ecdb764924a6c0652ca3e8c8211 (patch) | |
tree | 9eb73236c921378c46c5adb953246ba87d742a89 /src/import/chips/p9 | |
parent | 1b5008fbb99f5fdcc23b2b5e3ed105201aeb1132 (diff) | |
download | talos-hostboot-c9c3f24168195ecdb764924a6c0652ca3e8c8211.tar.gz talos-hostboot-c9c3f24168195ecdb764924a6c0652ca3e8c8211.zip |
CORE/CACHE: core/cache/l2_stopclocks Level 2
Change-Id: Iaffbe7d73cb7faa579daf4470f81d67bd03b9103
Original-Change-Id: Ie4bce2bcaf0ffb2d1e57370312c4536356b62efc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27338
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27583
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
4 files changed, 292 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C index 99b5c7b4e..4901b714e 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C @@ -26,7 +26,7 @@ // *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> // *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> // *HWP Team : PM -// *HWP Consumed by : HB:PREV +// *HWP Consumed by : HB:PERV // *HWP Level : 2 //------------------------------------------------------------------------------ @@ -36,12 +36,18 @@ #include <p9_misc_scom_addresses.H> #include <p9_quad_scom_addresses.H> #include <p9_hcd_common.H> +#include "p9_hcd_l2_stopclocks.H" #include "p9_hcd_cache_stopclocks.H" //------------------------------------------------------------------------------ // Constant Definitions //------------------------------------------------------------------------------ +enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS +{ + CACHE_CLK_STOP_TIMEOUT_IN_MS = 1 +}; + //------------------------------------------------------------------------------ // Procedure: Quad Clock Stop //------------------------------------------------------------------------------ @@ -49,11 +55,154 @@ fapi2::ReturnCode p9_hcd_cache_stopclocks( const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target, - const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS i_select_regions) + const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS i_select_regions, + const p9hcd::P9_HCD_EX_CTRL_CONSTANTS i_select_ex) { - FAPI_INF(">>p9_hcd_cache_stopclocks"); + FAPI_INF(">>p9_hcd_cache_stopclocks: regions[%x] ex[%d]", + i_select_regions, i_select_ex); + fapi2::buffer<uint64_t> l_data64; + uint32_t l_timeout; + uint64_t l_l3mask_pscom = 0; + uint8_t l_attr_chip_unit_pos = 0; + uint8_t l_attr_vdm_enable; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys; + auto l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + auto l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE, l_sys, + l_attr_vdm_enable)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET; + + if (i_select_regions & p9hcd::CLK_REGION_EX0_L3) + { + l_l3mask_pscom |= (BIT64(4) | BIT64(6) | BIT64(8)); + } + + if (i_select_regions & p9hcd::CLK_REGION_EX1_L3) + { + l_l3mask_pscom |= (BIT64(5) | BIT64(7) | BIT64(9)); + } + + // ----------------------------- + // Prepare to stop cache clocks + // ----------------------------- + /// @todo RTC158181 disable l2 snoop? disable lco? assert refresh quiesce? + + FAPI_DBG("Assert L3 pscom masks via RING_FENCE_MASK_LATCH_REG[4-9]"); + FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l3mask_pscom)); + + FAPI_DBG("Assert chiplet fence via NET_CTRL0[18]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(18))); + + // ------------------------------- + // Stop L2 clocks + // ------------------------------- + + FAPI_EXEC_HWP(fapi2::current_err, + p9_hcd_l2_stopclocks, + i_target, i_select_ex); + + // ------------------------------- + // Stop cache clocks + // ------------------------------- + + FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + + FAPI_DBG("Stop cache clocks via CLK_REGION"); + l_data64 = (p9hcd::CLK_STOP_CMD | + i_select_regions | + p9hcd::CLK_THOLD_ALL); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for cache clocks stopped via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CACHE_CLK_STOP_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSTOP_TIMEOUT() + .set_EQ_TARGET(i_target) + .set_EQCPLTSTAT(l_data64), + "Cache Clock Stop Timeout"); + + FAPI_DBG("Check cache clocks stopped"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); + + FAPI_ASSERT((((~l_data64) & i_select_regions) == 0), + fapi2::PMPROC_CACHECLKSTOP_FAILED() + .set_EQ_TARGET(i_target) + .set_EQCLKSTAT(l_data64), + "Cache Clock Stop Failed"); + FAPI_DBG("Cache clocks stopped now"); + + // ------------------------------- + // Fence up + // ------------------------------- + + FAPI_DBG("Assert vital fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3))); + + FAPI_DBG("Assert regional fences via CPLT_CTRL1[4-14]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, i_select_regions)); + + // ------------------------------- + // Disable VDM + // ------------------------------- + + if (l_attr_vdm_enable == fapi2::ENUM_ATTR_VDM_ENABLE_ON) + { + FAPI_DBG("Drop vdm enable via QPPM_VDMCR[0]"); + FAPI_TRY(putScom(i_target, EQ_PPM_VDMCR_CLEAR, MASK_SET(0))); + } + + // ------------------------------- + // Shutdown edram + // ------------------------------- + // QCCR[0/4] EDRAM_ENABLE_DC + // QCCR[1/5] EDRAM_VWL_ENABLE_DC + // QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC + // QCCR[3/7] EDRAM_VPP_ENABLE_DC + + if (i_select_regions & p9hcd::CLK_REGION_EX0_REFR) + { + FAPI_DBG("Sequence EX0 EDRAM disables via QPPM_QCCR[0-3]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(3))); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(2))); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(1))); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(0))); + } + + if (i_select_regions & p9hcd::CLK_REGION_EX1_REFR) + { + FAPI_DBG("Sequence EX1 EDRAM disables via QPPM_QCCR[4-7]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(7))); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(6))); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(5))); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(4))); + } + + // ------------------------------- + // Update QSSR and STOP history + // ------------------------------- + + FAPI_DBG("Set cache as stopped in QSSR"); + FAPI_TRY(putScom(l_chip, PU_OCB_OCI_QSSR_OR, + BIT64(l_attr_chip_unit_pos + 14))); + + FAPI_DBG("Set cache as stopped in STOP history register"); + FAPI_TRY(putScom(i_target, EQ_PPM_SSHSRC, (BIT64(0) | BIT64(13)))); + +fapi_try_exit: FAPI_INF("<<p9_hcd_cache_stopclocks"); - return fapi2::FAPI2_RC_SUCCESS; + return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H index 736b8b256..3c91c71c1 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H @@ -25,7 +25,7 @@ // *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> // *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> // *HWP Team : PM -// *HWP Consumed by : HB:PREV +// *HWP Consumed by : HB:PERV // *HWP Level : 2 #ifndef __P9_HCD_CACHE_STOPCLOCKS_H__ @@ -38,7 +38,8 @@ /// function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_hcd_cache_stopclocks_FP_t) ( const fapi2::Target<fapi2::TARGET_TYPE_EQ>&, - const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS); + const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS, + const p9hcd::P9_HCD_EX_CTRL_CONSTANTS); extern "C" { @@ -50,7 +51,8 @@ extern "C" fapi2::ReturnCode p9_hcd_cache_stopclocks( const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target, - const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS i_select_regions); + const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS i_select_regions, + const p9hcd::P9_HCD_EX_CTRL_CONSTANTS i_select_ex); } diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.mk b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.mk index 23c8c23f7..fe5f87211 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.mk +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.mk @@ -19,4 +19,5 @@ PROCEDURE=p9_hcd_cache_stopclocks $(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) OBJS+=p9_hcd_cache_stopclocks.o +OBJS+=p9_hcd_l2_stopclocks.o $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C index baa583f9e..532334609 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C @@ -42,6 +42,12 @@ // Constant Definitions //------------------------------------------------------------------------------ +enum P9_HCD_CORE_STOPCLOCKS_CONSTANTS +{ + CORE_CLK_SYNC_TIMEOUT_IN_MS = 1, + CORE_CLK_STOP_TIMEOUT_IN_MS = 1 +}; + //------------------------------------------------------------------------------ // Procedure: Core Clock Stop //------------------------------------------------------------------------------ @@ -51,9 +57,135 @@ p9_hcd_core_stopclocks( const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) { FAPI_INF(">>p9_hcd_core_stopclocks"); + fapi2::buffer<uint64_t> l_ccsr; + fapi2::buffer<uint64_t> l_data64; + uint32_t l_timeout; + uint8_t l_attr_chip_unit_pos; + uint8_t l_attr_vdm_enable; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys; + auto l_quad = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); + auto l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE, l_sys, + l_attr_vdm_enable)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = (l_attr_chip_unit_pos - + p9hcd::PERV_TO_CORE_POS_OFFSET) % 4; + + // ---------------------------- + // Prepare to stop core clocks + // ---------------------------- + + FAPI_DBG("Assert Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]"); + FAPI_TRY(putScom(l_quad, + (l_attr_chip_unit_pos < 2) ? + EX_0_CME_SCOM_SICR_OR : EX_1_CME_SCOM_SICR_OR, + (BIT64(6 + (l_attr_chip_unit_pos % 2)) | + BIT64(8 + (l_attr_chip_unit_pos % 2))))); + + FAPI_DBG("Assert chiplet fence via NET_CTRL0[18]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WOR, MASK_SET(18))); + + // ------------------------------- + // Stop core clocks + // ------------------------------- + + FAPI_DBG("Clear all SCAN_REGION_TYPE bits"); + FAPI_TRY(putScom(i_target, C_SCAN_REGION_TYPE, MASK_ZERO)); + + FAPI_DBG("Stop core clocks(all but pll) via CLK_REGION"); + l_data64 = (p9hcd::CLK_STOP_CMD | + p9hcd::CLK_REGION_ALL_BUT_PLL | + p9hcd::CLK_THOLD_ALL); + FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for core clocks stopped via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CORE_CLK_STOP_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CORECLKSTOP_TIMEOUT() + .set_CORE_TARGET(i_target) + .set_CORECPLTSTAT(l_data64), + "Core Clock Stop Timeout"); + + FAPI_DBG("Check core clocks stopped via CLOCK_STAT_SL[4-13]"); + FAPI_TRY(getScom(i_target, C_CLOCK_STAT_SL, l_data64)); + + FAPI_ASSERT((((~l_data64) & p9hcd::CLK_REGION_ALL_BUT_PLL) == 0), + fapi2::PMPROC_CORECLKSTOP_FAILED() + .set_CORE_TARGET(i_target) + .set_CORECLKSTAT(l_data64), + "Core Clock Stop Failed"); + FAPI_DBG("Core clocks stopped now"); + + // ------------------------------- + // Disable core clock sync + // ------------------------------- + + FAPI_DBG("Drop core clock sync enable via CPPM_CACCR[15]"); + FAPI_TRY(putScom(i_target, C_CPPM_CACCR_CLEAR, MASK_SET(15))); + + FAPI_DBG("Poll for core clock sync done to drop via CPPM_CACSR[13]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CORE_CLK_STOP_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, C_CPPM_CACSR, l_data64)); + } + while((l_data64.getBit<13>() == 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CORECLKSYNCDROP_TIMEOUT().set_COREPPMCACSR(l_data64), + "Core Clock Sync Drop Timeout"); + FAPI_DBG("Core clock sync done dropped"); + + // ------------------------------- + // Fence up + // ------------------------------- + + FAPI_DBG("Assert skew sense to skew adjust fence via NET_CTRL0[22]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WOR, MASK_SET(22))); + + FAPI_DBG("Assert vital fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_OR, MASK_SET(3))); + + FAPI_DBG("Assert regional fences via CPLT_CTRL1[4-14]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_OR, p9hcd::CLK_REGION_ALL)); + + /// @todo RTC158181 add DD1 attribute control + FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround"); + FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34))); + + // ------------------------------- + // Disable VDM + // ------------------------------- + + if (l_attr_vdm_enable == fapi2::ENUM_ATTR_VDM_ENABLE_ON) + { + FAPI_DBG("Drop vdm enable via CPPM_VDMCR[0]"); + FAPI_TRY(putScom(i_target, C_PPM_VDMCR_CLEAR, MASK_SET(0))); + } + + // ------------------------------- + // Update stop history + // ------------------------------- + + FAPI_DBG("Set core as stopped in STOP history register"); + FAPI_TRY(putScom(i_target, C_PPM_SSHSRC, (BIT64(0) | BIT64(13)))); + +fapi_try_exit: FAPI_INF("<<p9_hcd_core_stopclocks"); - return fapi2::FAPI2_RC_SUCCESS; + return fapi2::current_err; } |