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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-10-23 18:42:52 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-12-14 10:54:55 -0600 |
| commit | c95d3d86007024781a01759f20778c4fba671b18 (patch) | |
| tree | bec56e741711cb7a2a74e2525666918fc3db5b9d /src/import/chips/p9 | |
| parent | 9b441810e8d7a55a8427b3303ec8c6596b8b6963 (diff) | |
| download | talos-hostboot-c95d3d86007024781a01759f20778c4fba671b18.tar.gz talos-hostboot-c95d3d86007024781a01759f20778c4fba671b18.zip | |
Adds MRD coarse
Change-Id: Ibe1b416a21e9301d0fa6418a100a902346b2b2ed
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67914
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68574
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
3 files changed, 10 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index 5643e96db..ff834d9ae 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -278,7 +278,7 @@ fapi_try_exit: /// @param[in] i_target - the MCA target on which to operate /// @param[in] i_rp - the rank pair /// @param[in] i_abort_on_error - whether or not we are aborting on cal error -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok +/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok /// fapi2::ReturnCode mrep::pre_workaround( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index 65c2a9207..407e76a75 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -607,10 +607,6 @@ class mrep : public step }; -// TK:LRDIMM Identify if Host Interface Write Leveling (HWL) Mode needs to be updated or if the PHY can handle it -// TK:LRDIMM Identify if Host Interface Read Training is any different -// TK:LRDIMM Identify if Host Interface Write training Training is any different - /// /// @brief Sets data buffer training mode control word /// @param[in] i_target the DIMM target @@ -685,6 +681,7 @@ inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& fapi_try_exit: return fapi2::current_err; } + /// /// @brief Deconfigures calibration steps depending upon LRDIMM type /// @param[in] i_dimm_type - DIMM type diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index fc5629cea..b5561f322 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -58,6 +58,7 @@ #ifdef LRDIMM_CAPABLE #include <lib/phy/mss_dwl.H> + #include <lib/phy/mss_mrd_coarse.H> #include <lib/phy/mss_mrd_fine.H> #include <lib/phy/mss_mwd_coarse.H> #include <lib/phy/mss_mwd_fine.H> @@ -1227,6 +1228,13 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& #ifdef LRDIMM_CAPABLE + // MRD_COARSE + if(i_cal_steps.getBit<mss::cal_steps::MRD_COARSE>()) + { + FAPI_INF("LRDIMM: MRD_COARSE is enabled"); + l_steps.push_back(std::make_shared<mss::training::lrdimm::mrd_coarse>()); + } + // MRD_FINE if(i_cal_steps.getBit<mss::cal_steps::MRD_FINE>()) { |
