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| author | Rahul Batra <rbatra@us.ibm.com> | 2016-10-06 23:00:14 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-11-10 11:07:13 -0500 |
| commit | c52fc60516b6346cb06f05f438adb1c1c771e6b7 (patch) | |
| tree | acb1cb584b1752cbf694983e496b3837c4cd1dda /src/import/chips/p9 | |
| parent | 8053357f7fe7c6be1c624e3df04b608d2d4e765d (diff) | |
| download | talos-hostboot-c52fc60516b6346cb06f05f438adb1c1c771e6b7.tar.gz talos-hostboot-c52fc60516b6346cb06f05f438adb1c1c771e6b7.zip | |
PGPE: PState Updates
-Added code for Pstate Table generation and write it to HOMER
-Added temp. code to mimic boot process, i.e. copy Global Pstate
Parameter Block
-Added code to check for OCC_FLAG[PGPE_DEBUG_ENABLEMENT]
-Added code to write to PGPE beacon periodically using FIT
Change-Id: I8b2cee1b30d7ef56ee47a9432330a16c4cb1b989
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30850
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32400
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
3 files changed, 26 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h index 4ed35f8e5..6b20373d2 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h @@ -91,13 +91,21 @@ /// VPD #V Operating Points #define VPD_PV_POINTS 4 -#define VPD_PV_ORDER_STR {"PowerSave", "Nominal ", "Turbo ", "UltraTurbo"} +#define VPD_PV_ORDER_STR {"PowerSave ", "Nominal ", "Turbo ", "UltraTurbo"} #define POWERSAVE 1 #define NOMINAL 0 #define TURBO 2 #define ULTRA 3 #define POWERBUS 4 #define VPD_PV_ORDER {POWERSAVE, NOMINAL, TURBO, ULTRA} +#define VPD_NUM_SLOPES_SET 2 +#define VPD_SLOPES_RAW 0 +#define VPD_SLOPES_BIASED 1 +#define VPD_NUM_SLOPES_REGION 3 +#define REGION_POWERSAVE_NOMINAL 1 +#define REGION_NOMINAL_TURBO 0 +#define REGION_TURBO_ULTRA 2 + /// IDDQ readings, #define IDDQ_MEASUREMENTS 6 diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h index 0ecad6632..6b43819bd 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h @@ -218,6 +218,13 @@ typedef struct /// Resonant Clock Grid Management Setup ResonantClockingSetup resclk; + //Voltage change step size + uint32_t ext_vdd_step_size_mv; + + uint32_t nest_frequency_mhz; + + uint16_t PsVSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION]; + uint16_t VPsSlopes[VPD_NUM_SLOPES_SET][VPD_NUM_SLOPES_REGION]; // @todo DPLL Droop Settings. These need communication to SGPE for STOP } GlobalPstateParmBlock; diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h index a4432c4bd..e286f0991 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_table.h @@ -46,7 +46,8 @@ /// on the fly during Pstate protocol execution based on the Pstate Parameter /// Block content. -static const uint32_t MAX_PSTATE_TABLE_ENTRIES = 128; +#define MAX_PSTATE_TABLE_ENTRIES 128 +#define GEN_PSTATES_TBL_MAGIC 0x50535441424c3030 //PSTABL00 (last two ASCII characters indicate version number) #ifdef __cplusplus extern "C" { @@ -121,6 +122,14 @@ typedef struct /// as the raw_pstates content. PstateTable biased_pstates[MAX_PSTATE_TABLE_ENTRIES]; + ///VPD Operating points generated after applying biases + VpdOperatingPoint operating_points_biased[VPD_PV_POINTS]; + + ///VPD Operating points generated after applying system parameters + VpdOperatingPoint operating_points_sysp[VPD_PV_POINTS]; + + ///VPD Operating points generated after applying system parameters and biases + VpdOperatingPoint operating_points_biased_sysp[VPD_PV_POINTS]; } GeneratedPstateInfo; |
