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authorAbhishek Agarwal <abagarw8@in.ibm.com>2016-06-13 10:14:07 +0200
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-06-13 16:47:23 -0400
commita4edd934b26877603b9e024182d98fb210fba8fc (patch)
tree444595bab17fcded48e7fb2ae1de0130c8fca29f /src/import/chips/p9
parent29503be2a9bfa44d5edc361292cb3222ca6e353e (diff)
downloadtalos-hostboot-a4edd934b26877603b9e024182d98fb210fba8fc.tar.gz
talos-hostboot-a4edd934b26877603b9e024182d98fb210fba8fc.zip
Level 2 HWP p9_getecid
Change-Id: I0e1238fdd21e239bb082795ef7fad6fde3c3ebd9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25701 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25703 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_getecid.C68
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_getecid.H6
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml8
3 files changed, 75 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C b/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C
index ad2d909a8..077beb945 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_getecid.C
@@ -25,22 +25,84 @@
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
-// *HWP Level : 1
+// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
//## auto_generated
#include "p9_getecid.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_misc_scom_addresses_fld.H>
+#include <p9_const_common.H>
+enum P9_SBE_COMMON_Private_Constants
+{
+ OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT = 1 // OTPROM mode register MODE_ECC_ENABLE field/bit definitions
+};
fapi2::ReturnCode p9_getecid(const
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip, const fapi2::variable_buffer& o_fuseString)
+ fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip, fapi2::variable_buffer& o_fuseString)
{
+ uint64_t attr_data[2];
+ bool secure_mode = false;
+ fapi2::buffer<uint64_t> l_ecid_part0_data64 = 0;
+ fapi2::buffer<uint64_t> l_ecid_part1_data64 = 0;
+ fapi2::buffer<uint64_t> l_ecid_part1_data48 = 0;
+ fapi2::buffer<uint64_t> l_local = 0;
FAPI_INF("Entering ...");
+ FAPI_DBG("determine if security is enabled");
+ fapi2::buffer<uint64_t> l_data64;
+ FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64));
+ secure_mode = l_data64.getBit<4>();
+
+ FAPI_DBG("clear ECC enable before reading ECID data (read-modify-write OTPROM Mode register), insecure mode only");
+
+ if (!secure_mode)
+ {
+ fapi2::buffer<uint64_t> l_data64;
+ FAPI_TRY(fapi2::getScom(i_target_chip, PU_MODE_REGISTER, l_data64));
+ l_data64.clearBit<OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT>();
+ FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER, l_data64));
+ }
+
+ FAPI_DBG("extract and manipulate ECID data");
+ FAPI_TRY(fapi2::getScom(i_target_chip, PU_OTPROM0_ECID_PART0_REGISTER, l_ecid_part0_data64));
+ FAPI_TRY(fapi2::getScom(i_target_chip, PU_OTPROM0_ECID_PART1_REGISTER, l_ecid_part1_data64));
+ l_ecid_part0_data64.reverse();
+ l_ecid_part1_data64.reverse();
+
+ l_local.insertFromRight<0, 64>(l_ecid_part0_data64);
+ attr_data[0] = l_local;
+ l_local.insertFromRight<0, 64>(l_ecid_part1_data64);
+ attr_data[1] = l_local;
+ o_fuseString.insert(l_ecid_part0_data64, 0, 64, 0);
+ l_ecid_part1_data64.extractToRight<0, 48>(l_ecid_part1_data48);
+ o_fuseString.insert(l_ecid_part1_data48, 64, 48, 0);
+
+ FAPI_DBG("push fuse string into attribute");
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_ECID, i_target_chip, attr_data));
+
+ FAPI_DBG("restore ECC enable setting (insecure mode only)");
+
+ if (!secure_mode)
+ {
+ fapi2::buffer<uint64_t> l_data64;
+ FAPI_TRY(fapi2::getScom(i_target_chip, PU_MODE_REGISTER, l_data64));
+ l_data64.setBit<OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT>();
+ FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER, l_data64));
+ }
+
FAPI_INF("Exiting ...");
- return fapi2::FAPI2_RC_SUCCESS;
+// return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
+ return fapi2::current_err;
}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_getecid.H b/src/import/chips/p9/procedures/hwp/perv/p9_getecid.H
index 4a6e06387..2ea1779c3 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_getecid.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_getecid.H
@@ -25,7 +25,7 @@
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
-// *HWP Level : 1
+// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
@@ -38,7 +38,7 @@
typedef fapi2::ReturnCode (*p9_getecid_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
- const fapi2::variable_buffer& fuseString);
+ fapi2::variable_buffer& fuseString);
/// @brief Get ECID string from target using SCOM
///
@@ -47,7 +47,7 @@ typedef fapi2::ReturnCode (*p9_getecid_FP_t)(const fapi2::Target<fapi2::TARGET_T
extern "C"
{
fapi2::ReturnCode p9_getecid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
- const fapi2::variable_buffer& o_fuseString);
+ fapi2::variable_buffer& o_fuseString);
}
#endif
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index 5c91f196a..76091a0f9 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -348,8 +348,14 @@
<attribute>
<id>ATTR_ECID</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
- <description></description>
+ <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
+Created from running the mss_get_cen_ecid.C
+Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description>
<valueType>uint64</valueType>
+ <writeable/>
+ <odmVisable/>
+ <odmChangeable/>
+ <array> 2</array>
</attribute>
<attribute>
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