Chip address extension workaround for HW423589 (option2), part2

Change-Id: I175167f9f011e1da23b3f81a49d4ed5a2847b54d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49290
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49307
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

5 files changed, 741 insertions, 274 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
index aa6bd504e..46f11239f 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
@@ -120,6 +120,69 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
 
     fapi2::ReturnCode l_rc;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    uint8_t l_addr_extension_group_id = 0;
+    uint8_t l_addr_extension_chip_id = 0;
+    uint64_t l_max_interleave_group_size;
+    fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode = 0;
+    fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2 = 0;
+
+    auto l_targets = FAPI_SYSTEM.getChildren<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+    if (l_targets.size() != 0)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE,
+                               l_targets.front(),
+                               l_extended_addressing_mode),
+                 "Error from FAPI_ATTR_GET (fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)");
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2,
+                               l_targets.front(),
+                               l_hw423589_option2),
+                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)");
+
+        FAPI_DBG("Extended addressing supported: %d, HW423589 option2: %d",
+                 l_extended_addressing_mode,
+                 l_hw423589_option2);
+    }
+
+    if (l_extended_addressing_mode)
+    {
+        if (l_hw423589_option2)
+        {
+            l_addr_extension_group_id = CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2;
+            l_addr_extension_chip_id = CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2;
+        }
+
+        // enable extended addressing mode, seed attributes from defaults
+        // should allow for testing alternate configurations via Cronus with const
+        // attribute overrides
+        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                               FAPI_SYSTEM,
+                               l_addr_extension_group_id),
+                 "Error from FAPI_ATTR_SET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)");
+        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                               FAPI_SYSTEM,
+                               l_addr_extension_chip_id),
+                 "Error from FAPI_ATTR_SET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)");
+    }
+
+    if (l_hw423589_option2)
+    {
+        // restrict max size for MCD issue
+        l_max_interleave_group_size = MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2;
+    }
+    else
+    {
+        l_max_interleave_group_size = MAX_INTERLEAVE_GROUP_SIZE;
+    }
+
+    // store attribute in GB for direct comparison with group size attributes
+    l_max_interleave_group_size = l_max_interleave_group_size >> 30;
+
+    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MAX_INTERLEAVE_GROUP_SIZE,
+                           FAPI_SYSTEM,
+                           l_max_interleave_group_size),
+             "Error from FAPI_ATTR_SET (ATTR_MAX_INTERLEAVE_GROUP_SIZE)");
 
     // Get mirror placement policy
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY,
@@ -190,9 +253,12 @@ struct EffGroupingProcAttrs
         const EffGroupingSysAttrs i_sysAttrs);
 
     // Public data
-    uint64_t iv_memBaseAddr = 0;    // ATTR_PROC_MEM_BASE
-    uint64_t iv_mirrorBaseAddr = 0; // ATTR_PROC_MIRROR_BASE
-    uint64_t iv_nhtmBarSize;       // ATTR_PROC_NHTM_BAR_SIZE
+    std::vector<uint64_t> iv_memBaseAddr;    // ATTR_PROC_MEM_BASE
+    std::vector<uint64_t> iv_mirrorBaseAddr; // ATTR_PROC_MIRROR_BASE
+
+    uint64_t iv_maxGroupMemSize = 0;         // ATTR_MAX_INTERLEAVE_GROUP_SIZE
+
+    uint64_t iv_nhtmBarSize;                        // ATTR_PROC_NHTM_BAR_SIZE
     uint64_t iv_chtmBarSizes[NUM_OF_CHTM_REGIONS];  // ATTR_PROC_CHTM_BAR_SIZES
 
     uint64_t iv_occSandboxSize = 0; // ATTR_PROC_OCC_SANDBOX_SIZE
@@ -209,18 +275,21 @@ fapi2::ReturnCode EffGroupingProcAttrs::calcProcBaseAddr(
 {
     FAPI_DBG("Entering");
 
-    uint64_t l_memBaseAddr1, l_mmioBaseAddr;
+    std::vector<uint64_t> l_memBaseAddr1;
+    uint64_t l_mmioBaseAddr;
 
     // Get the Mirror/Non-mirror base addresses
-    FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target,
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
              EFF_FBC_GRP_CHIP_IDS,
              iv_memBaseAddr,
              l_memBaseAddr1,
              iv_mirrorBaseAddr,
              l_mmioBaseAddr),
-             "p9_fbc_utils_get_chip_base_address_no_aliases() returns an error, l_rc 0x%.8X",
+             "p9_fbc_utils_get_chip_base_address() returns an error, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
+    iv_memBaseAddr.insert(iv_memBaseAddr.end(), l_memBaseAddr1.begin(), l_memBaseAddr1.end());
+
 fapi_try_exit:
     FAPI_DBG("Exiting");
     return fapi2::current_err;
@@ -233,6 +302,12 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
 {
     FAPI_DBG("Entering EffGroupingProcAttrs::getAttrs");
 
+    // Get size (max) of each msel region
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MAX_INTERLEAVE_GROUP_SIZE,
+                           fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                           iv_maxGroupMemSize),
+             "Error from FAPI_ATTR_GET (ATTR_MAX_INTERLEAVE_GROUP_SIZE)");
+
     // Get Nest Hardware Trace Macro (NHTM) bar size
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NHTM_BAR_SIZE, i_target, iv_nhtmBarSize),
              "Error getting ATTR_PROC_HTM_BAR_SIZE, l_rc 0x%.8X",
@@ -286,8 +361,16 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
     FAPI_INF("  ATTR_PROC_FABRIC_SYSTEM_ID 0x%.8X", iv_fabricSystemId);
     FAPI_INF("  ATTR_PROC_FABRIC_GROUP_ID 0x%.8X", iv_fabricGroupId);
     FAPI_INF("  ATTR_PROC_FABRIC_CHIP_ID 0x%.8X", iv_fabricChipId);
-    FAPI_INF("  ATTR_PROC_MEM_BASE 0x%.16llX", iv_memBaseAddr);
-    FAPI_INF("  ATTR_PROC_MIRROR_BASE 0x%.16llX", iv_mirrorBaseAddr);
+
+    for (uint8_t ii = 0; ii < iv_memBaseAddr.size(); ii++)
+    {
+        FAPI_INF("  ATTR_PROC_MEM_BASE[%d] 0x%.16llX", ii, iv_memBaseAddr[ii]);
+    }
+
+    for (uint8_t ii = 0; ii < iv_mirrorBaseAddr.size(); ii++)
+    {
+        FAPI_INF("  ATTR_PROC_MIRROR_BASE[%d] 0x%.16llX", ii, iv_mirrorBaseAddr[ii]);
+    }
 
 fapi_try_exit:
     FAPI_DBG("Exiting EffGroupingProcAttrs::getAttrs");
@@ -519,6 +602,8 @@ struct EffGroupingMemInfo
     // Memory sizes behind MC ports
     uint32_t iv_portSize[NUM_MC_PORTS_PER_PROC];
 
+    // maximum group size which can be formed
+    uint64_t iv_maxGroupMemSize = 0;
 };
 
 // See doxygen in struct definition.
@@ -533,6 +618,13 @@ fapi2::ReturnCode EffGroupingMemInfo::getMemInfo (
     // Get the functional MCAs
     auto l_mcaChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCA>();
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MAX_INTERLEAVE_GROUP_SIZE,
+                           fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                           iv_maxGroupMemSize),
+             "Error from FAPI_ATTR_GET (ATTR_MAX_INTERLEAVE_GROUP_SIZE)");
+
+    FAPI_DBG("iv_maxGroupMemSize: 0x%016lX", iv_maxGroupMemSize);
+
     if (l_mcaChiplets.size() > 0)
     {
         FAPI_DBG("Number of MCAs found: %d", l_mcaChiplets.size());
@@ -592,7 +684,7 @@ fapi_try_exit:
 }
 
 ///----------------------------------------------------------------------------
-/// struct EffGroupingMemInfo
+/// struct EffGroupingData
 ///----------------------------------------------------------------------------
 ///
 /// @struct EffGroupingData
@@ -1417,13 +1509,13 @@ void grouping_group8PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
         }
 
         // Group of 8 is possible
-        if (grouped)
+        if (grouped &&
+            ((8 * i_memInfo.iv_portSize[0]) <= i_memInfo.iv_maxGroupMemSize))
         {
             // All 8 ports have same amount of memory, group them
             o_groupData.iv_data[g][PORT_SIZE] = i_memInfo.iv_portSize[0];
             o_groupData.iv_data[g][PORTS_IN_GROUP] = 8;
-            o_groupData.iv_data[g][GROUP_SIZE] =
-                (NUM_MC_PORTS_PER_PROC * i_memInfo.iv_portSize[0]);
+            o_groupData.iv_data[g][GROUP_SIZE] = (NUM_MC_PORTS_PER_PROC * i_memInfo.iv_portSize[0]);
             o_groupData.iv_data[g][MEMBER_IDX(0)] = MCPORTID_0;
             o_groupData.iv_data[g][MEMBER_IDX(1)] = MCPORTID_4;
             o_groupData.iv_data[g][MEMBER_IDX(2)] = MCPORTID_2;
@@ -1529,7 +1621,8 @@ void grouping_group6PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
         }
 
         // Group of 6 is possible
-        if (potential_group)
+        if (potential_group &&
+            ((PORTS_PER_GROUP * i_memInfo.iv_portSize[CFG_6MCPORT[ii][0]]) <= i_memInfo.iv_maxGroupMemSize))
         {
             o_groupData.iv_data[g][PORT_SIZE] =
                 i_memInfo.iv_portSize[CFG_6MCPORT[ii][0]];
@@ -1648,7 +1741,8 @@ void grouping_group4PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
         }
 
         // Group of 4 is possible
-        if (potential_group)
+        if (potential_group &&
+            ((PORTS_PER_GROUP * i_memInfo.iv_portSize[CFG_4MCPORT[ii][0]]) <= i_memInfo.iv_maxGroupMemSize))
         {
             FAPI_INF("    Potential group MC ports: MCPORTID %u, MCPORTID %u, MCPORTID %u, MCPORTID %u",
                      CFG_4MCPORT[ii][0], CFG_4MCPORT[ii][1],
@@ -1827,6 +1921,7 @@ void grouping_group3PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
         //    0 = OK to group
         //    1 = One of the ports has unequal amount of memory
         //    2 = 3rd entry port is odd and its even port has memory.
+        //    3 = group extent exceeds maximum size
         uint8_t l_canNotGroup = 0;
         uint8_t jj = 0;
 
@@ -1857,6 +1952,13 @@ void grouping_group3PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
                     break;
                 }
             }
+
+            if ((PORTS_PER_GROUP * i_memInfo.iv_portSize[CFG_3MCPORT[ii][0]]) >
+                i_memInfo.iv_maxGroupMemSize)
+            {
+                l_canNotGroup = 3;
+                break;
+            }
         }
 
         if (l_canNotGroup != 0) // Can not group 3 ports
@@ -1946,6 +2048,14 @@ void grouping_2ports_same_MCS(const EffGroupingMemInfo& i_memInfo,
             continue;
         }
 
+        if ((PORTS_PER_GROUP * i_memInfo.iv_portSize[pos]) >
+            i_memInfo.iv_maxGroupMemSize)
+        {
+            FAPI_DBG("Ports %u & %u can't be grouped because group size is too large, skip",
+                     pos, pos + 1);
+            continue;
+        }
+
         // Successfully find 2 ports on same MCS to group
         o_groupData.iv_data[g][PORT_SIZE] = i_memInfo.iv_portSize[pos];
         o_groupData.iv_data[g][PORTS_IN_GROUP] = PORTS_PER_GROUP;
@@ -2021,6 +2131,16 @@ void grouping_2groupsOf2_cross_MCS(const EffGroupingMemInfo& i_memInfo,
             continue;
         }
 
+        // only need to check size of 1st MCS (since the 2nd MCS would be the
+        // same size)
+        if ((PORTS_PER_GROUP * i_memInfo.iv_portSize[l_port]) >
+            i_memInfo.iv_maxGroupMemSize)
+        {
+            FAPI_DBG("Skip 1st MCS %u, as group size formed would be too large",
+                     mcs1);
+            continue;
+        }
+
         // Found first potential MCS, look for the 2nd MCS
         for (uint8_t mcs2 = mcs1 + 1; mcs2 < NUM_MCS_PER_PROC; mcs2++)
         {
@@ -2154,6 +2274,15 @@ void grouping_group2PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
             continue;
         }
 
+        // Skip if group size would be too large
+        if ((PORTS_PER_GROUP * i_memInfo.iv_portSize[pos]) >
+            i_memInfo.iv_maxGroupMemSize)
+        {
+            FAPI_DBG("Skip this port %u, as group size formed would be too large",
+                     pos);
+            continue;
+        }
+
         // Rules for group of 2 for remaining ports on cross-MCS
         // 1. Both ports must not be grouped yet and have the same amount of memory.
         // 2. For both ports, the other port in their MCS must be empty
@@ -2258,7 +2387,8 @@ void grouping_group1PortsPerGroup(const EffGroupingMemInfo& i_memInfo,
     for (uint8_t pos = 0; pos < NUM_MC_PORTS_PER_PROC; pos++)
     {
         if ( (!o_groupData.iv_portGrouped[pos]) &&
-             (i_memInfo.iv_portSize[pos] != 0) )
+             (i_memInfo.iv_portSize[pos] != 0) &&
+             (i_memInfo.iv_portSize[pos] <= i_memInfo.iv_maxGroupMemSize) )
         {
             // This MCS is not already grouped and has memory
             o_groupData.iv_data[g][PORT_SIZE] = i_memInfo.iv_portSize[pos];
@@ -2335,7 +2465,9 @@ fapi2::ReturnCode grouping_findUngroupedPorts(
         uint8_t l_mcPortNum = l_unGroupedPair.begin()->first;
         FAPI_ASSERT(false,
                     fapi2::MSS_EFF_GROUPING_UNABLE_TO_GROUP_MC()
-                    .set_MC_PORT(l_mcPortNum),
+                    .set_MC_PORT(l_mcPortNum)
+                    .set_MC_PORT_SIZE(i_memInfo.iv_portSize[l_mcPortNum])
+                    .set_MAX_REGION_SIZE(i_memInfo.iv_maxGroupMemSize),
                     "grouping_findUngroupedPorts: Unable to group port %u", l_mcPortNum);
     }
 
@@ -2549,166 +2681,232 @@ fapi_try_exit:
     return;
 }
 
+
 ///
-/// @brief Calculate Mirror Memory base and alt-base addresses
+/// @brief Calculate base and alt-base addresses
 ///
-/// @param[in] i_target           Reference to processor chip target
-/// @param[io] io_procAttrs       Processor Attributes (iv_mirrorBaseAddr can be
-///                                                     updated)
-/// @param[io] io_groupData       Group Data
-/// @param[in] i_totalSizeNonMirr Total non mirrored size
+/// @param[in] i_target     Reference to processor chip target
+/// @param[in] i_procAttrs  Processor Chip Attributes
+/// @param[in] i_cfgMirror  Map mirrored memory
+/// @param[io] io_groupData Group Data
 ///
 /// @return FAPI2_RC_SUCCESS if success, else error code.
 ///
-fapi2::ReturnCode grouping_calcMirrorMemory(
+fapi2::ReturnCode grouping_calcRegions(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
-    EffGroupingProcAttrs& io_procAttrs,
+    const EffGroupingProcAttrs& i_procAttrs,
+    const bool i_cfgMirror,
     EffGroupingData& io_groupData)
 {
     FAPI_DBG("Entering");
 
-    // Calculate mirrored group size and non mirrored group size
-    for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
+    // index for region which is used for mapping current group
+    // group size should never exceed the size of a particular
+    // region (enforced by restricting group size at formation time)
+    // if current group will stack on top of the prior group & not overflow
+    // the region, stack it, else place in next region
+    uint8_t l_cur_nm_region_idx = 0;
+    uint8_t l_cur_m_region_idx = 0;
+    uint8_t l_max_nm_region_idx = 0;
+    uint8_t l_max_m_region_idx = 0;
+    uint64_t l_nm_region_size_left = i_procAttrs.iv_maxGroupMemSize;
+    uint64_t l_m_region_size_left = i_procAttrs.iv_maxGroupMemSize / 2;
+    uint64_t l_cur_m_base_addr = 0;
+
+    if (i_procAttrs.iv_memBaseAddr.size())
+    {
+        l_max_nm_region_idx = i_procAttrs.iv_memBaseAddr.size() - 1;
+    }
+
+    if (i_procAttrs.iv_mirrorBaseAddr.size())
+    {
+        l_max_m_region_idx = i_procAttrs.iv_mirrorBaseAddr.size() - 1;
+    }
+
+    // Calculate mirrored group sizes
+    if (i_cfgMirror)
     {
-        if (io_groupData.iv_mirrorOn[pos])
+        l_cur_m_base_addr = i_procAttrs.iv_mirrorBaseAddr[l_cur_m_region_idx];
+
+        for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
         {
-            uint8_t l_mirrorOffset = pos + MIRR_OFFSET;
-
-            // Mirrored size is half the group size
-            io_groupData.iv_data[l_mirrorOffset][GROUP_SIZE] =
-                io_groupData.iv_data[pos][GROUP_SIZE] / 2;
-            io_groupData.iv_data[l_mirrorOffset][PORT_SIZE] =
-                io_groupData.iv_data[pos][PORT_SIZE];
-            io_groupData.iv_data[l_mirrorOffset][PORTS_IN_GROUP] =
-                io_groupData.iv_data[pos][PORTS_IN_GROUP];
-
-            // Copy port members fron non-mirrored to mirrored group
-            for (uint8_t ii = 0; ii < io_groupData.iv_data[pos][PORTS_IN_GROUP]; ii++)
+            if (io_groupData.iv_mirrorOn[pos])
             {
-                io_groupData.iv_data[l_mirrorOffset][MEMBER_IDX(ii)] =
-                    io_groupData.iv_data[pos][MEMBER_IDX(ii)];
-            }
+                uint8_t l_mirrorOffset = pos + MIRR_OFFSET;
+
+                // Mirrored size is half the group size
+                io_groupData.iv_data[l_mirrorOffset][GROUP_SIZE] =
+                    io_groupData.iv_data[pos][GROUP_SIZE] / 2;
+                io_groupData.iv_data[l_mirrorOffset][PORT_SIZE] =
+                    io_groupData.iv_data[pos][PORT_SIZE];
+                io_groupData.iv_data[l_mirrorOffset][PORTS_IN_GROUP] =
+                    io_groupData.iv_data[pos][PORTS_IN_GROUP];
+
+                // Copy port members fron non-mirrored to mirrored group
+                for (uint8_t ii = 0; ii < io_groupData.iv_data[pos][PORTS_IN_GROUP]; ii++)
+                {
+                    io_groupData.iv_data[l_mirrorOffset][MEMBER_IDX(ii)] =
+                        io_groupData.iv_data[pos][MEMBER_IDX(ii)];
+                }
 
-            for (uint8_t l_altRegion = 0; l_altRegion < NUM_OF_ALT_MEM_REGIONS; l_altRegion++)
-            {
-                if (io_groupData.iv_data[pos][ALT_VALID(l_altRegion)])
+                for (uint8_t l_altRegion = 0; l_altRegion < NUM_OF_ALT_MEM_REGIONS; l_altRegion++)
                 {
-                    FAPI_INF("Mirrored group %u needs alt bars definition, group size %u GB",
-                             pos, io_groupData.iv_data[pos][GROUP_SIZE]);
-                    io_groupData.iv_data[l_mirrorOffset][ALT_SIZE(l_altRegion)] =
-                        io_groupData.iv_data[pos][ALT_SIZE(l_altRegion)] / 2;
-                    io_groupData.iv_data[l_mirrorOffset][ALT_VALID(l_altRegion)] = 1;
+                    if (io_groupData.iv_data[pos][ALT_VALID(l_altRegion)])
+                    {
+                        FAPI_INF("Mirrored group %u needs alt bars definition, group size %u GB",
+                                 pos, io_groupData.iv_data[pos][GROUP_SIZE]);
+                        io_groupData.iv_data[l_mirrorOffset][ALT_SIZE(l_altRegion)] =
+                            io_groupData.iv_data[pos][ALT_SIZE(l_altRegion)] / 2;
+                        io_groupData.iv_data[l_mirrorOffset][ALT_VALID(l_altRegion)] = 1;
+                    }
                 }
             }
         }
     }
 
-    // Convert base addresses to GB for calculation
-    uint64_t memBaseAddr_GB = io_procAttrs.iv_memBaseAddr >> 30;
-    uint64_t mirrorBaseAddr_GB = io_procAttrs.iv_mirrorBaseAddr >> 30;
-    FAPI_DBG("io_procAttrs.iv_memBaseAddr 0x%.16llX, memBaseAddr_GB 0x%.16llX", io_procAttrs.iv_memBaseAddr,
-             memBaseAddr_GB);
-    FAPI_DBG("io_procAttrs.iv_mirrorBaseAddr 0x%.16llX, mirrorBaseAddr_GB 0x%.16llX", io_procAttrs.iv_mirrorBaseAddr,
-             mirrorBaseAddr_GB);
-    FAPI_DBG("io_groupData.iv_totalSizeNonMirr %d", io_groupData.iv_totalSizeNonMirr);
-
-    // Check if the memory base address overlaps with the mirror base address
-    if ( (memBaseAddr_GB > (mirrorBaseAddr_GB + (io_groupData.iv_totalSizeNonMirr / 2))) ||
-         (mirrorBaseAddr_GB > (memBaseAddr_GB + io_groupData.iv_totalSizeNonMirr)) )
+    // Assign non-mirroring base address for each group
+    for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
     {
-        // No overlapping
-        for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
+        bool l_map_mirror = i_cfgMirror &&
+                            (io_groupData.iv_data[pos][PORTS_IN_GROUP] > 1);
+
+        // first group goes in first region
+        if (pos == 0)
         {
-            if (pos == 0)
+            FAPI_ASSERT((l_cur_nm_region_idx < l_max_nm_region_idx) &&
+                        (l_nm_region_size_left >=
+                         io_groupData.iv_data[pos][GROUP_SIZE]),
+                        fapi2::MSS_EFF_GROUPING_NM_REGION_MAP_ERROR()
+                        .set_PROC_CHIP(i_target)
+                        .set_MEM_BASE_ADDRS(i_procAttrs.iv_memBaseAddr)
+                        .set_CURR_GROUP_IDX(pos)
+                        .set_CURR_GROUP_SIZE(io_groupData.iv_data[pos][GROUP_SIZE])
+                        .set_CURR_REGION_IDX(l_cur_nm_region_idx)
+                        .set_CURR_REGION_SIZE_LEFT(l_nm_region_size_left)
+                        .set_MAX_REGION_IDX(l_max_nm_region_idx)
+                        .set_MAX_REGION_SIZE(i_procAttrs.iv_maxGroupMemSize),
+                        "Unable to map non-mirrored group!");
+
+            FAPI_ASSERT(!l_map_mirror ||
+                        ((l_cur_m_region_idx < l_max_m_region_idx) &&
+                         (l_m_region_size_left >=
+                          io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE])),
+                        fapi2::MSS_EFF_GROUPING_M_REGION_MAP_ERROR()
+                        .set_PROC_CHIP(i_target)
+                        .set_MIRROR_BASE_ADDRS(i_procAttrs.iv_memBaseAddr)
+                        .set_CURR_GROUP_IDX(pos)
+                        .set_CURR_GROUP_SIZE(io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE])
+                        .set_CURR_REGION_IDX(l_cur_m_region_idx)
+                        .set_CURR_REGION_SIZE_LEFT(l_m_region_size_left)
+                        .set_MAX_REGION_IDX(l_max_m_region_idx)
+                        .set_MAX_REGION_SIZE(i_procAttrs.iv_maxGroupMemSize / 2),
+                        "Unable to map mirrored group!");
+
+            // assign non mirrored base address
+            io_groupData.iv_data[pos][BASE_ADDR] =
+                (i_procAttrs.iv_memBaseAddr[l_cur_nm_region_idx] >> 30);
+
+            // assign mirrored base address
+            if (l_map_mirror)
             {
-                // Note:
-                // The 2nd memory hole was intended for use with 12Gb DRAM parts,
-                // which we do not have to support - so it will not be used in Nimbus.
-                io_groupData.iv_data[pos][BASE_ADDR] = memBaseAddr_GB;
+                io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] =
+                    l_cur_m_base_addr >> 30;
             }
-            else
+        }
+        else
+        {
+            if (l_nm_region_size_left >= io_groupData.iv_data[pos][GROUP_SIZE])
             {
+                // stack on top of last region mapped
                 io_groupData.iv_data[pos][BASE_ADDR] =
                     io_groupData.iv_data[pos - 1][BASE_ADDR] +
                     io_groupData.iv_data[pos - 1][GROUP_SIZE];
-            }
 
-            // Note:
-            // The 2nd memory hole was intended for use with 12Gb DRAM parts,
-            // which we do not have to support - so it will not be used in Nimbus.
-            if (io_groupData.iv_data[pos][ALT_VALID(0)])
-            {
-                io_groupData.iv_data[pos][ALT_BASE_ADDR(0)] =
-                    io_groupData.iv_data[pos][BASE_ADDR] +
-                    io_groupData.iv_data[pos][GROUP_SIZE] -
-                    io_groupData.iv_data[pos][ALT_SIZE(0)];
+                if (l_map_mirror)
+                {
+                    // should have space to map mirrored group if non-mirrored
+                    // group fits, assert
+                    FAPI_ASSERT((l_m_region_size_left >=
+                                 io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE]),
+                                fapi2::MSS_EFF_GROUPING_M_REGION_MAP_ERROR()
+                                .set_PROC_CHIP(i_target)
+                                .set_MIRROR_BASE_ADDRS(i_procAttrs.iv_memBaseAddr)
+                                .set_CURR_GROUP_IDX(pos)
+                                .set_CURR_GROUP_SIZE(io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE])
+                                .set_CURR_REGION_IDX(l_cur_m_region_idx)
+                                .set_CURR_REGION_SIZE_LEFT(l_m_region_size_left)
+                                .set_MAX_REGION_IDX(l_max_m_region_idx)
+                                .set_MAX_REGION_SIZE(i_procAttrs.iv_maxGroupMemSize / 2),
+                                "Unable to map mirrored group!");
+                    io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] =
+                        l_cur_m_base_addr >> 30;
+                }
             }
-
-            if (io_groupData.iv_data[pos][PORTS_IN_GROUP] > 1)
+            else
             {
-                io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] = mirrorBaseAddr_GB;
-                mirrorBaseAddr_GB += io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE];
-                io_procAttrs.iv_mirrorBaseAddr = (mirrorBaseAddr_GB << 30);
+                // move to next region (mirrored/non-mirrored)
+                l_cur_nm_region_idx++;
+                l_cur_m_region_idx++;
+
+                // reset available size variables
+                l_nm_region_size_left = i_procAttrs.iv_maxGroupMemSize;
+                l_m_region_size_left = i_procAttrs.iv_maxGroupMemSize / 2;
+
+                // assert that mappings are valid
+                FAPI_ASSERT((l_cur_nm_region_idx < l_max_nm_region_idx) &&
+                            (l_nm_region_size_left >=
+                             io_groupData.iv_data[pos][GROUP_SIZE]),
+                            fapi2::MSS_EFF_GROUPING_NM_REGION_MAP_ERROR()
+                            .set_PROC_CHIP(i_target)
+                            .set_MEM_BASE_ADDRS(i_procAttrs.iv_memBaseAddr)
+                            .set_CURR_GROUP_IDX(pos)
+                            .set_CURR_GROUP_SIZE(io_groupData.iv_data[pos][GROUP_SIZE])
+                            .set_CURR_REGION_IDX(l_cur_nm_region_idx)
+                            .set_CURR_REGION_SIZE_LEFT(l_nm_region_size_left)
+                            .set_MAX_REGION_IDX(l_max_nm_region_idx)
+                            .set_MAX_REGION_SIZE(i_procAttrs.iv_maxGroupMemSize),
+                            "Unable to map non-mirrored group!");
+
+                FAPI_ASSERT(!l_map_mirror ||
+                            ((l_cur_m_region_idx < l_max_m_region_idx) &&
+                             (l_m_region_size_left >=
+                              io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE])),
+                            fapi2::MSS_EFF_GROUPING_M_REGION_MAP_ERROR()
+                            .set_PROC_CHIP(i_target)
+                            .set_MIRROR_BASE_ADDRS(i_procAttrs.iv_memBaseAddr)
+                            .set_CURR_GROUP_IDX(pos)
+                            .set_CURR_GROUP_SIZE(io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE])
+                            .set_CURR_REGION_IDX(l_cur_m_region_idx)
+                            .set_CURR_REGION_SIZE_LEFT(l_m_region_size_left)
+                            .set_MAX_REGION_IDX(l_max_m_region_idx)
+                            .set_MAX_REGION_SIZE(i_procAttrs.iv_maxGroupMemSize / 2),
+                            "Unable to map mirrored group!");
+
+                // reset mirror base address
+                l_cur_m_base_addr = i_procAttrs.iv_mirrorBaseAddr[l_cur_m_region_idx];
+
+                // assign non mirrored base address
+                io_groupData.iv_data[pos][BASE_ADDR] =
+                    (i_procAttrs.iv_memBaseAddr[l_cur_nm_region_idx] >> 30);
 
-                if (io_groupData.iv_data[pos][ALT_VALID(0)])
+                // assign mirrored base address
+                if (l_map_mirror)
                 {
-                    io_groupData.iv_data[pos + MIRR_OFFSET][ALT_BASE_ADDR(0)] = io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] +
-                            io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE] / 2;
-                    io_groupData.iv_data[pos + MIRR_OFFSET][ALT_VALID(0)] = 1;
+                    io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] =
+                        l_cur_m_base_addr >> 30;
                 }
-
-                FAPI_DBG("Adjust Mirror Base Address for group %d", pos);
-                FAPI_DBG("New values: io_procAttrs.iv_mirrorBaseAddr 0x%.16llX, mirrorBaseAddr_GB 0x%.16llX",
-                         io_procAttrs.iv_mirrorBaseAddr, mirrorBaseAddr_GB);
-                FAPI_DBG("Mirror group size: io_groupData.iv_data[%d][GROUP_SIZE] = %d", pos + MIRR_OFFSET,
-                         io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE]);
-                FAPI_DBG("Mirror group base addr: io_groupData.iv_data[%d][BASE_ADDR] = 0x%.16llX", pos + MIRR_OFFSET,
-                         io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR]);
             }
         }
-    }
-    else
-    {
-        FAPI_ASSERT(false,
-                    fapi2::MSS_EFF_GROUPING_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS()
-                    .set_PROC_CHIP(i_target)
-                    .set_MEM_BASE_ADDR(io_procAttrs.iv_memBaseAddr)
-                    .set_MIRROR_BASE_ADDR(io_procAttrs.iv_mirrorBaseAddr)
-                    .set_SIZE_NON_MIRROR(io_groupData.iv_totalSizeNonMirr),
-                    "Mirror Base address overlaps with memory base address");
-    }
 
-fapi_try_exit:
-    FAPI_DBG("Exiting");
-    return fapi2::current_err;
-}
+        // update remaining size in region
+        l_nm_region_size_left -= io_groupData.iv_data[pos][GROUP_SIZE];
+        l_m_region_size_left -= (io_groupData.iv_data[pos][GROUP_SIZE] / 2);
 
-///
-/// @brief Calculate Non-mirror Memory base and alt-base addresses
-///
-/// @param[in] i_procAttrs  Processor Chip Attributes
-/// @param[io] io_groupData Group Data
-///
-void grouping_calcNonMirrorMemory(const EffGroupingProcAttrs& i_procAttrs,
-                                  EffGroupingData& io_groupData)
-{
-    FAPI_DBG("Entering");
-
-    // Assign mirroring and non-mirroring base address for each group
-    for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
-    {
-        if (pos == 0)
-        {
-            io_groupData.iv_data[pos][BASE_ADDR] =
-                (i_procAttrs.iv_memBaseAddr >> 30);
-        }
-        else
-        {
-            io_groupData.iv_data[pos][BASE_ADDR] =
-                io_groupData.iv_data[pos - 1][BASE_ADDR] +
-                io_groupData.iv_data[pos - 1][GROUP_SIZE];
-        }
+        // increment mirrored address (regardless of whether mapped
+        // for this group)
+        l_cur_m_base_addr += io_groupData.iv_data[pos][GROUP_SIZE] / 2;
 
+        // set alt region information directly based on base region mapping
         for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++)
         {
             if (io_groupData.iv_data[pos][ALT_VALID(ii)])
@@ -2717,12 +2915,21 @@ void grouping_calcNonMirrorMemory(const EffGroupingProcAttrs& i_procAttrs,
                     io_groupData.iv_data[pos][BASE_ADDR] +
                     io_groupData.iv_data[pos][GROUP_SIZE] -
                     io_groupData.iv_data[pos][ALT_SIZE(ii)];
+
+                if (l_map_mirror)
+                {
+                    io_groupData.iv_data[pos + MIRR_OFFSET][ALT_BASE_ADDR(ii)] =
+                        io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] +
+                        io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE] / 2;
+                    io_groupData.iv_data[pos + MIRR_OFFSET][ALT_VALID(ii)] = 1;
+                }
             }
         }
     }
 
+fapi_try_exit:
     FAPI_DBG("Exiting");
-    return;
+    return fapi2::current_err;
 }
 
 ///
@@ -2987,21 +3194,13 @@ fapi2::ReturnCode p9_mss_eff_grouping(
         }
     }
 
-    if (l_mirrorIsOn)
-    {
-        FAPI_INF("Mirror memory configured");
-        // Calculate base and alt-base addresses
-        FAPI_TRY(grouping_calcMirrorMemory(i_target, l_procAttrs, l_groupData),
-                 "Error from grouping_calcMirrorMemory, l_rc 0x%.8X",
-                 (uint64_t)fapi2::current_err);
-    }
-    else
-    {
-        // ATTR_MRW_HW_MIRRORING_ENABLE is false
-        // Calculate base and alt-base addresses
-        FAPI_INF("No mirror memory configured");
-        grouping_calcNonMirrorMemory(l_procAttrs, l_groupData);
-    }
+    FAPI_INF("Mapping groups to regions (mirroring=%s)",
+             (l_mirrorIsOn ? ("enabled") : ("disabled")));
+
+    // Calculate base and alt-base addresses
+    FAPI_TRY(grouping_calcRegions(i_target, l_procAttrs, l_mirrorIsOn, l_groupData),
+             "Error from grouping_calcRegions, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
 
     // Set the ATTR_MSS_MEM_MC_IN_GROUP attribute
     FAPI_TRY(grouping_setATTR_MSS_MEM_MC_IN_GROUP(i_target, l_groupData),
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
index 7223b2098..25f5281a3 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C
@@ -69,13 +69,13 @@ p9_setup_bars_build_chip_info(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
 {
     FAPI_DBG("Start");
 
-    FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target,
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
              EFF_FBC_GRP_CHIP_IDS,
-             io_chip_info.base_address_nm[0],
-             io_chip_info.base_address_nm[1],
+             io_chip_info.base_address_nm0,
+             io_chip_info.base_address_nm1,
              io_chip_info.base_address_m,
              io_chip_info.base_address_mmio),
-             "Error from p9_fbc_utils_get_chip_base_address_no_aliases");
+             "Error from p9_fbc_utils_get_chip_base_address");
 
     FAPI_TRY(p9_fbc_utils_get_group_id_attr(i_target,
                                             io_chip_info.fbc_group_id),
@@ -85,6 +85,16 @@ p9_setup_bars_build_chip_info(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                                            io_chip_info.fbc_chip_id),
              "Error from p9_fbc_utils_get_chip_id_attr");
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE,
+                           i_target,
+                           io_chip_info.extended_addressing_mode),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2,
+                           i_target,
+                           io_chip_info.hw423589_option2),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)");
+
 fapi_try_exit:
     FAPI_DBG("End");
     return fapi2::current_err;
@@ -143,6 +153,151 @@ fapi_try_exit:
 }
 
 
+///
+/// @brief Enable MCD units 0/1
+///
+/// @param[in] i_target Processor chip target
+/// @param[in] i_target_sys System target
+/// @param[in] i_chip_info Structure describing chip properties/base addresses
+///
+/// @return FAPI_RC_SUCCESS if all calls are successful, else error
+fapi2::ReturnCode
+p9_setup_bars_mcd_enable(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target_sys,
+    p9_setup_bars_chip_info& i_chip_info)
+{
+    FAPI_DBG("Start");
+
+    uint8_t l_addr_extension_group_id = 0;
+    uint8_t l_addr_extension_chip_id = 0;
+    fapi2::buffer<uint64_t> l_fir_data = 0;
+    fapi2::buffer<uint64_t> l_mcd_rec_data = 0;
+    fapi2::buffer<uint64_t> l_mcd_vgc_data = 0;
+
+    // configure FIR
+    // clear FIR
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCC_FIR_REG, l_fir_data),
+             "Error from putScom (PU_MCC_FIR_REG)");
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCC_FIR_REG, l_fir_data),
+             "Error from putScom (PU_MCD1_MCC_FIR_REG)");
+    // set action
+    l_fir_data = MCD_FIR_ACTION0;
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_ACTION0_REG, l_fir_data),
+             "Error from putScom (PU_MCD_FIR_ACTION0_REG)");
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_ACTION0_REG, l_fir_data),
+             "Error from putScom (PU_MCD1_MCD_FIR_ACTION0_REG)");
+    l_fir_data = MCD_FIR_ACTION1;
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_ACTION1_REG, l_fir_data),
+             "Error from putScom (PU_MCD_FIR_ACTION1_REG)");
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_ACTION1_REG, l_fir_data),
+             "Error from putScom (PU_MCD1_MCD_FIR_ACTION1_REG)");
+    // set mask
+    l_fir_data = MCD_FIR_MASK;
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_MASK_REG, l_fir_data),
+             "Error from putScom (PU_MCD_FIR_MASK_REG)");
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_MASK_REG, l_fir_data),
+             "Error from putScom (PU_MCD1_MCD_FIR_MASK_REG)");
+
+    if (i_chip_info.extended_addressing_mode)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                               i_target_sys,
+                               l_addr_extension_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)");
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                               i_target_sys,
+                               l_addr_extension_chip_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID");
+    }
+
+    // set MCD vectored group configuration register
+    FAPI_TRY(fapi2::getScom(i_target, PU_BANK0_MCD_VGC, l_mcd_vgc_data),
+             "Error from getScom (PU_BANK0_MCD_VGC)");
+
+    if (l_addr_extension_group_id ||
+        l_addr_extension_chip_id)
+    {
+        l_mcd_vgc_data.setBit<P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_ENABLE>();
+        l_mcd_vgc_data.insertFromRight<P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK,
+                                       P9N2_PU_BANK0_MCD_VGC_EXT_ADDR_FAC_MASK_LEN>((l_addr_extension_group_id << 3) |
+                                               l_addr_extension_chip_id);
+    }
+
+    l_mcd_vgc_data.insertFromRight<PU_BANK0_MCD_VGC_AVAIL_GROUPS, PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN>(MCD_VGC_AVAIL_GROUPS);
+    l_mcd_vgc_data.setBit<PU_BANK0_MCD_VGC_HANG_POLL_ENABLE>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_BANK0_MCD_VGC, l_mcd_vgc_data),
+             "Error from putScom (PU_BANK0_MCD_VGC)");
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_BANK0_MCD_VGC, l_mcd_vgc_data),
+             "Error from putScom (PU_MCD1_BANK0_MCD_VGC)");
+
+    // enable MCD probes
+    l_mcd_rec_data.setBit<PU_BANK0_MCD_REC_ENABLE>();
+    l_mcd_rec_data.setBit<PU_BANK0_MCD_REC_CONTINUOUS>();
+    l_mcd_rec_data.insertFromRight<PU_BANK0_MCD_REC_PACE, PU_BANK0_MCD_REC_PACE_LEN>(MCD_RECOVERY_PACE_RATE);
+    l_mcd_rec_data.insertFromRight<PU_BANK0_MCD_REC_RTY_COUNT, PU_BANK0_MCD_REC_RTY_COUNT_LEN>(MCD_RECOVERY_RTY_COUNT);
+    l_mcd_rec_data.insertFromRight<PU_BANK0_MCD_REC_VG_COUNT, PU_BANK0_MCD_REC_VG_COUNT_LEN>(MCD_RECOVERY_VG_COUNT);
+    FAPI_TRY(fapi2::putScom(i_target, PU_BANK0_MCD_REC, l_mcd_rec_data),
+             "Error from putScom (PU_BANK0_MCD_REC)");
+    FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_BANK0_MCD_REC, l_mcd_rec_data),
+             "Error from putScom (PU_MCD1_BANK0_MCD_REC)");
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+
+/// @brief Program MCD units 0/1 to track non-mirrored regions
+///        of real address space on this chip, for HW423589_OPTION2
+///
+/// @param[in] i_target Processor chip target
+/// @param[in] i_target_sys System target
+/// @param[in] i_chip_info Structure describing chip properties/base addresses
+///
+/// @return FAPI_RC_SUCCESS if all calls are successful, else error
+fapi2::ReturnCode
+p9_setup_bars_mcd_HW423589_OPTION2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                                   const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target_sys,
+                                   p9_setup_bars_chip_info& i_chip_info)
+{
+    FAPI_DBG("Start");
+    p9_setup_bars_addr_range l_nm_cover;
+    uint64_t l_cover_size = MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 / 2;
+
+    // setup two MCD configurations
+    // chip msel0 base       [ size=256 GB ]
+    // chip msel0 base + 256 [ size=256 GB ]
+    l_nm_cover.enabled = true;
+    l_nm_cover.base_addr = i_chip_info.base_address_nm0.front();
+    l_nm_cover.size = l_cover_size;
+
+    FAPI_TRY(p9_setup_bars_mcd_track_range(i_target,
+                                           l_nm_cover,
+                                           PU_MCD1_BANK0_MCD_TOP,
+                                           PU_BANK0_MCD_TOP),
+             "Error from p9_setup_bars_mcd_track_range (0)");
+
+    l_nm_cover.base_addr += l_cover_size;
+
+    FAPI_TRY(p9_setup_bars_mcd_track_range(i_target,
+                                           l_nm_cover,
+                                           PU_MCD1_BANK0_MCD_STR,
+                                           PU_BANK0_MCD_STR),
+             "Error from p9_setup_bars_mcd_track_range (1)");
+
+    FAPI_TRY(p9_setup_bars_mcd_enable(i_target,
+                                      i_target_sys,
+                                      i_chip_info),
+             "Error from p9_setup_bars_mcd_enable");
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+
 /// @brief Program MCD units 0/1 to track non-mirrored and mirrored regions
 ///        of real address space on this chip
 ///
@@ -157,9 +312,10 @@ p9_setup_bars_mcd(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
                   p9_setup_bars_chip_info& i_chip_info)
 {
     FAPI_DBG("Start");
-    p9_setup_bars_addr_range l_nm_range[2];
-    p9_setup_bars_addr_range l_m_range;
-    bool l_enable_mcd = false;
+    std::vector<p9_setup_bars_addr_range> l_nm_ranges[2];
+    std::vector<p9_setup_bars_addr_range> l_m_ranges;
+    bool l_enable_mcd_nm = false;
+    bool l_enable_mcd_m = false;
     fapi2::ATTR_MRW_HW_MIRRORING_ENABLE_Type l_mirror_ctl;
 
     // determine range of NM memory which MCD needs to cover on this chip
@@ -167,12 +323,26 @@ p9_setup_bars_mcd(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
         fapi2::ATTR_PROC_MEM_BASES_ACK_Type l_nm_bases;
         fapi2::ATTR_PROC_MEM_SIZES_ACK_Type l_nm_sizes;
 
+        // initialize set of ranges -- track the number of mappable regions
+        // in each msel
+        for (uint8_t ii = 0; ii < i_chip_info.base_address_nm0.size(); ii++)
+        {
+            p9_setup_bars_addr_range r;
+            l_nm_ranges[0].push_back(r);
+        }
+
+        for (uint8_t ii = 0; ii < i_chip_info.base_address_nm1.size(); ii++)
+        {
+            p9_setup_bars_addr_range r;
+            l_nm_ranges[1].push_back(r);
+        }
+
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_MEM_BASES_ACK, i_target, l_nm_bases),
                  "Error fram FAPI_ATTR_GET (ATTR_PROC_MEM_BASES_ACK)");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_MEM_SIZES_ACK, i_target, l_nm_sizes),
                  "Error fram FAPI_ATTR_GET (ATTR_PROC_MEM_SIZES_ACK)");
 
-        // add each valid NM group range to its associated NM chip range
+        // add each valid NM group to its associated NM chip range
         for (uint8_t ll = 0; ll < NUM_NON_MIRROR_REGIONS; ll++)
         {
             p9_setup_bars_addr_range l_range(l_nm_bases[ll],
@@ -180,51 +350,109 @@ p9_setup_bars_mcd(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
 
             if (l_range.enabled)
             {
-                l_enable_mcd = true;
-
-                // determine which NM range (0/1) this range is associated with
-                if (l_range.base_addr < i_chip_info.base_address_nm[1])
+                FAPI_DBG("Adding group: %d", ll);
+                l_range.print();
+
+                bool l_range_placed = false;
+                l_enable_mcd_nm = true;
+
+                // determine which msel (nm0/nm1) the region lies within
+                // then determine which NM range this range is associated with
+                // find first range (walking backwards through the sorted
+                // list) for which the starting address of this range is
+                // greater than the base address
+                if ((i_chip_info.base_address_nm1.size() != 0) &&
+                    l_range.base_addr >= i_chip_info.base_address_nm1[0])
                 {
-                    l_nm_range[0].merge(l_range);
+                    // nm1
+                    for (int jj = i_chip_info.base_address_nm1.size() - 1;
+                         (jj >= 0) && !l_range_placed;
+                         jj--)
+                    {
+                        if (l_range.base_addr >= i_chip_info.base_address_nm1[jj])
+                        {
+                            l_nm_ranges[1][jj].merge(l_range);
+                            l_range_placed = true;
+                        }
+                    }
                 }
                 else
                 {
-                    l_nm_range[1].merge(l_range);
+                    // nm0
+                    for (int jj = i_chip_info.base_address_nm0.size() - 1;
+                         (jj >= 0) && !l_range_placed;
+                         jj--)
+                    {
+                        if (l_range.base_addr >= i_chip_info.base_address_nm0[jj])
+                        {
+                            l_nm_ranges[0][jj].merge(l_range);
+                            l_range_placed = true;
+                        }
+                    }
                 }
+
+                // check for consistency -- should always find a match
+                FAPI_ASSERT(l_range_placed,
+                            fapi2::P9_SETUP_BARS_INVALID_MCD_NM_RANGE_ERR().
+                            set_TARGET(i_target).
+                            set_NM_RANGE_IDX(ll).
+                            set_NM_RANGE_BASE_ADDR(l_nm_bases[ll]).
+                            set_NM_RANGE_SIZE(l_nm_sizes[ll]).
+                            set_NM0_CHIP_BASES(i_chip_info.base_address_nm0).
+                            set_NM1_CHIP_BASES(i_chip_info.base_address_nm1),
+                            "Invalid configuration for MCD NM range!");
             }
         }
 
-        // process each NM chip range
-        for (uint8_t l_nm_range_idx = 0; l_nm_range_idx < 2; l_nm_range_idx++)
+        // generate independent cover for each of the two msels
+        for (uint8_t ii = 0; ii < 2; ii++)
         {
-            if (l_nm_range[l_nm_range_idx].enabled)
+            if (l_nm_ranges[ii].size() != 0)
             {
-                // ensure power of two alignment
-                if (!l_nm_range[l_nm_range_idx].is_power_of_2())
+                FAPI_DBG("Generating MCD cover for NM msel %d",
+                         ii);
+
+                p9_setup_bars_addr_range l_nm_cover;
+                l_nm_cover.base_addr = l_nm_ranges[ii][0].base_addr;
+
+                FAPI_DBG("  Cover base address: 0x%016lX",
+                         l_nm_cover.base_addr);
+
+                for (uint8_t jj = 0; jj < l_nm_ranges[ii].size(); jj++)
                 {
-                    l_nm_range[l_nm_range_idx].round_next_power_of_2();
+                    if (l_nm_ranges[ii][jj].enabled)
+                    {
+                        FAPI_DBG("  Processing valid range %d, base addr: 0x%016lX, size: 0x%016lX",
+                                 jj, l_nm_ranges[ii][jj].base_addr, l_nm_ranges[ii][jj].size);
+
+                        l_nm_cover.enabled = true;
+
+                        // ensure power of two alignment
+                        if (!l_nm_ranges[ii][jj].is_power_of_2())
+                        {
+                            l_nm_ranges[ii][jj].round_next_power_of_2();
+                        }
+
+                        i_chip_info.ranges.push_back(l_nm_ranges[ii][jj]);
+                        i_chip_info.ranges.back().print();
+                    }
+
+                    // need to cover size of largest alias region
+                    if (l_nm_cover.size < l_nm_ranges[ii][jj].size)
+                    {
+                        l_nm_cover.size = l_nm_ranges[ii][jj].size;
+                        FAPI_DBG("  Updating cover size: 0x%016lX",
+                                 l_nm_cover.size);
+                    }
                 }
 
-                // verify that base lines up with chip info struct
-                FAPI_ASSERT(l_nm_range[l_nm_range_idx].base_addr == i_chip_info.base_address_nm[l_nm_range_idx],
-                            fapi2::P9_SETUP_BARS_INVALID_MCD_NM_RANGE_ERR().
-                            set_TARGET(i_target).
-                            set_NM_RANGE_IDX(l_nm_range_idx).
-                            set_NM_RANGE_BASE_ADDR(l_nm_range[l_nm_range_idx].base_addr).
-                            set_NM_RANGE_SIZE(l_nm_range[l_nm_range_idx].size).
-                            set_NM_CHIP_BASE(i_chip_info.base_address_nm[l_nm_range_idx]),
-                            "Invalid configuration for MCD NM range!");
-
                 // configure MCD to track this range
-                //   range 0 = MCD_BOT, range 1 = MCD_STR
+                //   nm0 = MCD_BOT, nm1 = MCD_STR
                 FAPI_TRY(p9_setup_bars_mcd_track_range(i_target,
-                                                       l_nm_range[l_nm_range_idx],
-                                                       ((l_nm_range_idx == 0) ? (PU_MCD1_BANK0_MCD_BOT) : (PU_MCD1_BANK0_MCD_STR)),
-                                                       ((l_nm_range_idx == 0) ? (PU_BANK0_MCD_BOT) : (PU_BANK0_MCD_STR))),
-                         "Error from p9_setup_bars_mcd_track_range (NM%d)", l_nm_range_idx);
-
-                i_chip_info.ranges.push_back(l_nm_range[l_nm_range_idx]);
-                i_chip_info.ranges.back().print();
+                                                       l_nm_cover,
+                                                       ((ii == 0) ? (PU_MCD1_BANK0_MCD_BOT) : (PU_MCD1_BANK0_MCD_STR)),
+                                                       ((ii == 0) ? (PU_BANK0_MCD_BOT) : (PU_BANK0_MCD_STR))),
+                         "Error from p9_setup_bars_mcd_track_range (NM%d)", ii);
             }
         }
     }
@@ -236,15 +464,24 @@ p9_setup_bars_mcd(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
 
     if (l_mirror_ctl == fapi2::ENUM_ATTR_MRW_HW_MIRRORING_ENABLE_TRUE)
     {
-
         fapi2::ATTR_PROC_MIRROR_BASES_ACK_Type l_m_bases;
         fapi2::ATTR_PROC_MIRROR_SIZES_ACK_Type l_m_sizes;
+        p9_setup_bars_addr_range l_m_cover;
+
+        // initialize set of ranges -- track the number of mappable
+        // regions
+        for (uint8_t ii = 0; ii < i_chip_info.base_address_m.size(); ii++)
+        {
+            p9_setup_bars_addr_range r;
+            l_m_ranges.push_back(r);
+        }
+
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_MIRROR_BASES_ACK, i_target, l_m_bases),
                  "Error fram FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASES_ACK)");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_MIRROR_SIZES_ACK, i_target, l_m_sizes),
                  "Error fram FAPI_ATTR_GET (ATTR_PROC_MIRROR_SIZES_ACK)");
 
-        // add each valid M group range to the M chip range
+        // add each valid M group range to its associated M chip range
         for (uint8_t ll = 0; ll < NUM_MIRROR_REGIONS; ll++)
         {
             p9_setup_bars_addr_range l_range(l_m_bases[ll],
@@ -252,91 +489,81 @@ p9_setup_bars_mcd(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
 
             if (l_range.enabled)
             {
-                l_enable_mcd = true;
-                l_m_range.merge(l_range);
+                bool l_range_placed = false;
+                l_enable_mcd_m = true;
+
+                // determine which M range this range is associated with
+                // find first range (walking backwards through the sorted
+                // list) for which the starting address of this range is
+                // greater than the base address
+                for (int jj = i_chip_info.base_address_m.size() - 1;
+                     (jj >= 0) && !l_range_placed;
+                     jj--)
+                {
+                    if (l_range.base_addr >= i_chip_info.base_address_m[jj])
+                    {
+                        l_m_ranges[jj].merge(l_range);
+                        l_range_placed = true;
+                    }
+                }
+
+                // check for consistency -- should always find a match
+                FAPI_ASSERT(l_range_placed,
+                            fapi2::P9_SETUP_BARS_INVALID_MCD_M_RANGE_ERR().
+                            set_TARGET(i_target).
+                            set_M_RANGE_IDX(ll).
+                            set_M_RANGE_BASE_ADDR(l_m_bases[ll]).
+                            set_M_RANGE_SIZE(l_m_sizes[ll]).
+                            set_M_CHIP_BASES(i_chip_info.base_address_m),
+                            "Invalid configuration for MCD M range!");
             }
         }
 
-        // process M chip range
-        if (l_m_range.enabled)
+        // process each merged range, find the largest which the MCD needs to
+        // cover -- all aliases will be covered by the MCD config reg programmed
+        if (l_enable_mcd_m)
         {
-            // ensure power of two alignment
-            if (!l_m_range.is_power_of_2())
+            l_m_cover.enabled = true;
+            l_m_cover.base_addr = l_m_ranges[0].base_addr;
+
+            for (uint8_t jj = 0; jj < l_m_ranges.size(); jj++)
             {
-                l_m_range.round_next_power_of_2();
-            }
+                if (l_m_ranges[jj].enabled)
+                {
+                    // ensure power of two alignment
+                    if (!l_m_ranges[jj].is_power_of_2())
+                    {
+                        l_m_ranges[jj].round_next_power_of_2();
+                    }
+
+                    i_chip_info.ranges.push_back(l_m_ranges[jj]);
+                    i_chip_info.ranges.back().print();
+                }
 
-            // verify that base lines up with chip info struct
-            FAPI_ASSERT(l_m_range.base_addr == i_chip_info.base_address_m,
-                        fapi2::P9_SETUP_BARS_INVALID_MCD_M_RANGE_ERR().
-                        set_TARGET(i_target).
-                        set_M_RANGE_BASE_ADDR(l_m_range.base_addr).
-                        set_M_RANGE_SIZE(l_m_range.size).
-                        set_M_CHIP_BASE(i_chip_info.base_address_m),
-                        "Invalid configuration for MCD M range!");
+                // need to cover size of largest alias
+                if (l_m_cover.size < l_m_ranges[jj].size)
+                {
+                    l_m_cover.size = l_m_ranges[jj].size;
+                }
+            }
 
-            // configure MCD to track this range (MCD_TOP)
+            // configure MCD to track this range via MCD_TOP
             FAPI_TRY(p9_setup_bars_mcd_track_range(i_target,
-                                                   l_m_range,
+                                                   l_m_cover,
                                                    PU_MCD1_BANK0_MCD_TOP,
                                                    PU_BANK0_MCD_TOP),
                      "Error from p9_setup_bars_mcd_track_range (M)");
-
-            i_chip_info.ranges.push_back(l_m_range);
-            i_chip_info.ranges.back().print();
         }
     }
 
     // if configured above to track any NM or M space, perform the remainder
     // of the MCD setup (FIR configuration, probe enablement)
-    if (l_enable_mcd)
+    if (l_enable_mcd_nm || l_enable_mcd_m)
     {
-        fapi2::buffer<uint64_t> l_fir_data = 0;
-        fapi2::buffer<uint64_t> l_mcd_rec_data = 0;
-        fapi2::buffer<uint64_t> l_mcd_vgc_data = 0;
-
-        // configure FIR
-        // clear FIR
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCC_FIR_REG, l_fir_data),
-                 "Error from putScom (PU_MCC_FIR_REG)");
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCC_FIR_REG, l_fir_data),
-                 "Error from putScom (PU_MCD1_MCC_FIR_REG)");
-        // set action
-        l_fir_data = MCD_FIR_ACTION0;
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_ACTION0_REG, l_fir_data),
-                 "Error from putScom (PU_MCD_FIR_ACTION0_REG)");
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_ACTION0_REG, l_fir_data),
-                 "Error from putScom (PU_MCD1_MCD_FIR_ACTION0_REG)");
-        l_fir_data = MCD_FIR_ACTION1;
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_ACTION1_REG, l_fir_data),
-                 "Error from putScom (PU_MCD_FIR_ACTION1_REG)");
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_ACTION1_REG, l_fir_data),
-                 "Error from putScom (PU_MCD1_MCD_FIR_ACTION1_REG)");
-        // set mask
-        l_fir_data = MCD_FIR_MASK;
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD_FIR_MASK_REG, l_fir_data),
-                 "Error from putScom (PU_MCD_FIR_MASK_REG)");
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_MCD_FIR_MASK_REG, l_fir_data),
-                 "Error from putScom (PU_MCD1_MCD_FIR_MASK_REG)");
-
-        // set MCD vectored group configuration
-        l_mcd_vgc_data.insertFromRight<PU_BANK0_MCD_VGC_AVAIL_GROUPS, PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN>(MCD_VGC_AVAIL_GROUPS);
-        l_mcd_vgc_data.setBit<PU_BANK0_MCD_VGC_HANG_POLL_ENABLE>();
-        FAPI_TRY(fapi2::putScom(i_target, PU_BANK0_MCD_VGC, l_mcd_vgc_data),
-                 "Error from putScom (PU_BANK0_MCD_VGC)");
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_BANK0_MCD_VGC, l_mcd_vgc_data),
-                 "Error from putScom (PU_MCD1_BANK0_MCD_VGC)");
-
-        // enable MCD probes
-        l_mcd_rec_data.setBit<PU_BANK0_MCD_REC_ENABLE>();
-        l_mcd_rec_data.setBit<PU_BANK0_MCD_REC_CONTINUOUS>();
-        l_mcd_rec_data.insertFromRight<PU_BANK0_MCD_REC_PACE, PU_BANK0_MCD_REC_PACE_LEN>(MCD_RECOVERY_PACE_RATE);
-        l_mcd_rec_data.insertFromRight<PU_BANK0_MCD_REC_RTY_COUNT, PU_BANK0_MCD_REC_RTY_COUNT_LEN>(MCD_RECOVERY_RTY_COUNT);
-        l_mcd_rec_data.insertFromRight<PU_BANK0_MCD_REC_VG_COUNT, PU_BANK0_MCD_REC_VG_COUNT_LEN>(MCD_RECOVERY_VG_COUNT);
-        FAPI_TRY(fapi2::putScom(i_target, PU_BANK0_MCD_REC, l_mcd_rec_data),
-                 "Error from putScom (PU_BANK0_MCD_REC)");
-        FAPI_TRY(fapi2::putScom(i_target, PU_MCD1_BANK0_MCD_REC, l_mcd_rec_data),
-                 "Error from putScom (PU_MCD1_BANK0_MCD_REC)");
+        FAPI_TRY(p9_setup_bars_mcd_enable(i_target,
+                                          i_target_sys,
+                                          i_chip_info),
+                 "Error from p9_setup_bars_mcd_enable");
     }
 
 fapi_try_exit:
@@ -1020,8 +1247,19 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
              "Error from p9_setup_bars_npu");
 
     // MCD
-    FAPI_TRY(p9_setup_bars_mcd(i_target, FAPI_SYSTEM, l_chip_info),
-             "Error from p9_setup_bars_mcd");
+    if (l_chip_info.extended_addressing_mode && l_chip_info.hw423589_option2)
+    {
+        FAPI_TRY(p9_setup_bars_mcd_HW423589_OPTION2(i_target,
+                 FAPI_SYSTEM,
+                 l_chip_info),
+                 "Error from p9_setup_bars_mcd_HW423589_OPTION2");
+    }
+    else
+    {
+        FAPI_TRY(p9_setup_bars_mcd(i_target, FAPI_SYSTEM, l_chip_info),
+                 "Error from p9_setup_bars_mcd");
+    }
+
     // INT
     FAPI_TRY(p9_setup_bars_int(i_target, FAPI_SYSTEM, l_chip_info),
              "Error from p9_setup_bars_int");
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
index 36c71fb23..84500f122 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
@@ -43,7 +43,7 @@
 #include <fapi2.H>
 #include <p9_fbc_utils.H>
 #include <p9_misc_scom_addresses.H>
-
+#include <p9n2_misc_scom_addresses_fld.H>
 
 //------------------------------------------------------------------------------
 // Structure definitions
@@ -289,10 +289,13 @@ struct p9_setup_bars_chip_info
 {
     uint8_t fbc_group_id;
     uint8_t fbc_chip_id;
-    uint64_t base_address_nm[2];
-    uint64_t base_address_m;
+    std::vector<uint64_t> base_address_nm0;
+    std::vector<uint64_t> base_address_nm1;
+    std::vector<uint64_t> base_address_m;
     uint64_t base_address_mmio;
     std::vector<p9_setup_bars_addr_range> ranges;
+    uint8_t hw423589_option2;
+    uint8_t extended_addressing_mode;
 };
 
 //------------------------------------------------------------------------------
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
index 7f5344769..13f2aba9e 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
@@ -64,6 +64,8 @@
         This is a memory plugging error. Refer to memory plugging rules.
     </description>
     <ffdc>MC_PORT</ffdc>
+    <ffdc>MC_PORT_SIZE</ffdc>
+    <ffdc>MAX_REGION_SIZE</ffdc>
     <callout>
         <procedure>MEMORY_PLUGGING_ERROR</procedure>
         <priority>HIGH</priority>
@@ -108,15 +110,39 @@
 </hwpError>
 
 <hwpError>
-    <rc>RC_MSS_EFF_GROUPING_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS</rc>
+    <rc>RC_MSS_EFF_GROUPING_NM_REGION_MAP_ERROR</rc>
     <description>
-        p9_mss_eff_grouping found that the base address overlaps with the
-        mirror base address.
+        p9_mss_eff_grouping did not find an available region
+	to map non-mirrored group
     </description>
     <ffdc>PROC_CHIP</ffdc>
-    <ffdc>MEM_BASE_ADDR</ffdc>
-    <ffdc>MIRROR_BASE_ADDR</ffdc>
-    <ffdc>SIZE_NON_MIRROR</ffdc>
+    <ffdc>MEM_BASE_ADDRS</ffdc>
+    <ffdc>CURR_GROUP_IDX</ffdc>
+    <ffdc>CURR_GROUP_SIZE</ffdc>
+    <ffdc>CURR_REGION_IDX</ffdc>
+    <ffdc>CURR_REGION_SIZE_LEFT</ffdc>
+    <ffdc>MAX_REGION_IDX</ffdc>
+    <ffdc>MAX_REGION_SIZE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+</hwpError>
+
+<hwpError>
+    <rc>RC_MSS_EFF_GROUPING_M_REGION_MAP_ERROR</rc>
+    <description>
+        p9_mss_eff_grouping did not find an available region
+	to map mirrored group
+    </description>
+    <ffdc>PROC_CHIP</ffdc>
+    <ffdc>MIRROR_BASE_ADDRS</ffdc>
+    <ffdc>CURR_GROUP_IDX</ffdc>
+    <ffdc>CURR_GROUP_SIZE</ffdc>
+    <ffdc>CURR_REGION_IDX</ffdc>
+    <ffdc>CURR_REGION_SIZE_LEFT</ffdc>
+    <ffdc>MAX_REGION_IDX</ffdc>
+    <ffdc>MAX_REGION_SIZE</ffdc>
     <callout>
       <procedure>CODE</procedure>
       <priority>HIGH</priority>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_setup_bars_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_setup_bars_errors.xml
index ddcac8321..657da4205 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_setup_bars_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_setup_bars_errors.xml
@@ -114,7 +114,8 @@
     <ffdc>NM_RANGE_IDX</ffdc>
     <ffdc>NM_RANGE_BASE_ADDR</ffdc>
     <ffdc>NM_RANGE_SIZE</ffdc>
-    <ffdc>NM_CHIP_BASE</ffdc>
+    <ffdc>NM0_CHIP_BASES</ffdc>
+    <ffdc>NM1_CHIP_BASES</ffdc>
     <callout>
       <procedure>CODE</procedure>
       <priority>HIGH</priority>
@@ -131,7 +132,7 @@
     <ffdc>M_RANGE_IDX</ffdc>
     <ffdc>M_RANGE_BASE_ADDR</ffdc>
     <ffdc>M_RANGE_SIZE</ffdc>
-    <ffdc>M_CHIP_BASE</ffdc>
+    <ffdc>M_CHIP_BASES</ffdc>
     <callout>
       <procedure>CODE</procedure>
       <priority>HIGH</priority>