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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-01-04 20:45:43 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-01-19 16:31:19 -0500 |
| commit | 59062a6fbb722e55d204b2b7a1e0eaaf095932a0 (patch) | |
| tree | ae8fac1f3b3589b1612f7a480faea0eaa4dc05ba /src/import/chips/p9 | |
| parent | 647e0daddc89a131bce9ebae754aff4ca343e45b (diff) | |
| download | talos-hostboot-59062a6fbb722e55d204b2b7a1e0eaaf095932a0.tar.gz talos-hostboot-59062a6fbb722e55d204b2b7a1e0eaaf095932a0.zip | |
add SS PLL settings to support 94 MHz PCI operation
support PCIE on DD1.x by lowering input refclock
Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34470
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index e87bd4f5a..a8fb979a0 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -426,6 +426,24 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 only: leverage SS PLL to provide reduced frequency reference clock + (94 MHz, instead of nominal 100 MHz) for PCI PLL + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ******************************************************************** --> <!-- Memory Section --> |
