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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2018-09-25 01:27:30 -0500 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-12-14 15:13:33 -0600 |
commit | 55a180dc08f9e9a837672ebae03a92dd9bba3ef9 (patch) | |
tree | 10b8c4a3e7a2a420720a4af459d3ca06151af3a2 /src/import/chips/p9 | |
parent | 2ad30a4a4e4db7bc8d3b015e408848f70c3014f8 (diff) | |
download | talos-hostboot-55a180dc08f9e9a837672ebae03a92dd9bba3ef9.tar.gz talos-hostboot-55a180dc08f9e9a837672ebae03a92dd9bba3ef9.zip |
Self Save: Fixed bugs pertaining to SPR self save.
Commit fixes some issues with code found during integration test
- replacement of addi with xor instruction during self save API.
- fixing instruction generation for MFMSR during self save
- data struct updates in STOP API
- error RC updates for hcode image build
- HOMER parser updates.
- removed self save support for URMOR and HRMOR
- code changes for compilation with OPAL
- populating CME Image header with unsecure HOMER address.
Key_Cronus_Test=PM_REGRESS
Change-Id: I7cedcc466267c4245255d8d75c01ed695e316720
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66580
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66587
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
8 files changed, 191 insertions, 35 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 03f37b8e4..e248c6d64 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -304,6 +304,7 @@ HCD_HDR_UINT16(g_cme_location_id, 0); HCD_HDR_UINT16(g_cme_qm_mode_flags, 0); HCD_HDR_UINT32(g_cme_timebase_hz, 0); //Retain next field at 8B boundary HCD_HDR_UINT64(g_cme_cpmr_PhyAddr, 0); +HCD_HDR_UINT64(g_cme_unsec_cpmr_PhyAddr, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H b/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H index 3266fdefe..79b4e9597 100755 --- a/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_stop_util.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -95,7 +95,10 @@ typedef struct uint64_t cpmrMagicWord; uint32_t buildDate; uint32_t version; - uint8_t reserve1[7]; + uint8_t reserve1[4]; + uint8_t selfRestoreVer; + uint8_t stopApiVer; + uint8_t urmorFix; uint8_t fusedModeStatus; uint32_t cmeImgOffset; uint32_t cmeImgLength; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 38d4debac..d72c4d7bd 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -58,6 +58,7 @@ #ifdef __CRONUS_VER #include <string> #endif + using namespace stopImageSection; extern "C" @@ -141,6 +142,8 @@ enum SMF_SELF_REST_SIGN_OFFSET = 0x1300, SMF_SELF_SIGNATURE = 0x5f534d46, CORE_REST_WORDS_PER_THREAD = (CORE_RESTORE_SIZE_PER_THREAD >> 2), + TWO_MB_ALIGNMENT_CHECK = 0x1FFFFF, + SMF_BIT_CHECK = 0x0001000000000000ull, }; /** @@ -1355,6 +1358,7 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); FAPI_INF(" Timebase (Hz) : 0x%08X (%d)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_timebase_hz), SWIZZLE_4_BYTE(pCmeHdr->g_cme_timebase_hz)); + FAPI_INF(" UnSecure HOMER : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_unsec_cpmr_PhyAddr)); FAPI_INF("========================= CME Header End =================================="); FAPI_INF("==========================CPMR Header==========================================="); @@ -4707,6 +4711,98 @@ fapi_try_exit: //--------------------------------------------------------------------------- + fapi2::ReturnCode verifySprSelfSave( void * i_pHomer, uint8_t i_fuseMode, + P9FuncModel & i_chipFuncModel ) +{ + #ifdef __SELF_SAVE_TEST + uint64_t l_pir = 0; + uint32_t l_saveVect = 0; + l_saveVect = + ( 0x80000000 >> BIT_POS_CIABR ) | + ( 0x80000000 >> BIT_POS_DAWR ) | + ( 0x80000000 >> BIT_POS_DAWRX ) | + ( 0x80000000 >> BIT_POS_HSPRG0) | + ( 0x80000000 >> BIT_POS_LDBAR ) | + ( 0x80000000 >> BIT_POS_LPCR ) | + ( 0x80000000 >> BIT_POS_MSR ) | + ( 0x80000000 >> BIT_POS_HID ) | + ( 0x80000000 >> BIT_POS_HMEER ) | + ( 0x80000000 >> BIT_POS_PTCR ) | + ( 0x80000000 >> BIT_POS_SMFCTRL) | + ( 0x80000000 >> BIT_POS_USPRG0 ) | + ( 0x80000000 >> BIT_POS_USPRG1 ) | + ( 0x80000000 >> BIT_POS_PMCR ) ; + + StopReturnCode_t l_rc; + + FAPI_DBG( "Save Vector 0x%08x" , l_saveVect ); + + for( uint8_t l_corePos = 0; l_corePos < MAX_CORES_PER_CHIP; + l_corePos++ ) + { + if( i_chipFuncModel.isCoreFunctional( l_corePos ) ) + { + for( uint8_t l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; + l_threadPos++ ) + { + l_pir = getPirValue( l_corePos, l_threadPos, i_fuseMode ); + l_rc = stopImageSection::p9_stop_save_cpureg_control( i_pHomer, + l_pir, l_saveVect ); + FAPI_ASSERT( ( !l_rc ), + fapi2::SELF_SAVE_API_FAILED() + .set_PIR( l_pir ) + .set_STOP_API_RC( l_rc ) + .set_CORE_POS( l_corePos ) + .set_THREAD_POS( l_threadPos ), + "Failed To Create SPR Self Save Entry" ); + } + } + } + + fapi_try_exit: + #endif + return fapi2::current_err; +} + +//--------------------------------------------------------------------------- + +fapi2::ReturnCode populateUnsecureHomerAddress( CONST_FAPI2_PROC& i_procTgt, Homerlayout_t* i_pHomer ) +{ + uint64_t l_unsecureHomerAdd = 0; + uint8_t l_invalidAddress = 0; + cmeHeader_t* pCmeHdr = + (cmeHeader_t*) & i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + FAPI_DBG( ">> populateUnsecureHomerAddress" ); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_UNSECURE_HOMER_ADDRESS, + i_procTgt, + l_unsecureHomerAdd), + "Error from FAPI_ATTR_GET for attribute ATTR_UNSECURE_HOMER_ADDRESS"); + FAPI_INF( "Atrribute ATTR_UNSECURE_HOMER_ADDRESS 0x%016lx", l_unsecureHomerAdd ); + + if( l_unsecureHomerAdd & 0x1fffff ) + { + l_invalidAddress = 1; + } + else if( (l_unsecureHomerAdd & SMF_BIT_CHECK) ) + { + l_invalidAddress = 1; + } + + FAPI_ASSERT( ( !l_invalidAddress ), + fapi2::BAD_UNSECURE_HOMER_VALUE() + .set_UNSECURE_HOMER_ADDRESS( l_unsecureHomerAdd ), + "Bad address for unsecure HOMER 0x%016lx", l_unsecureHomerAdd ); + + pCmeHdr->g_cme_unsec_cpmr_PhyAddr = SWIZZLE_8_BYTE(l_unsecureHomerAdd); + + fapi_try_exit: + FAPI_DBG( "<< populateUnsecureHomerAddress" ); + return fapi2::current_err; +} + +//-------------------------------------------------------------------------------------------------------- + fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, void* const i_pImageIn, void* i_pHomerImage, @@ -4883,9 +4979,13 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, l_riskLevel, l_qpmrHdr, i_imgType ), "Failed To Layout Quad Rings" ); + FAPI_TRY( populateUnsecureHomerAddress( i_procTgt, pChipHomer ), + "Failed To Populate Unsecure HOMER Region with sc2 instruction" ); + //Update CPMR Header with Scan Ring details updateCpmrCmeRegion( pChipHomer ); + //Update QPMR Header area in HOMER updateQpmrHeader( pChipHomer, l_qpmrHdr ); @@ -4934,6 +5034,9 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, FAPI_TRY( addUrmorRestore( i_pHomerImage, fuseModeState, l_chipFuncModel ), "Failed to create URMOR restore entry" ); + FAPI_TRY( verifySprSelfSave( i_pHomerImage, fuseModeState, l_chipFuncModel ), + "Failed to create SPR self save restore entry" ); + fapi_try_exit: FAPI_IMP("<< p9_hcode_image_build" ); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H b/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H index dd4358a82..27603b23f 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H @@ -68,6 +68,7 @@ enum MFSPR_CONST = 339, BLR_INST = 0x4e800020, MTSPR_BASE_OPCODE = 0x7c0003a6, + MFSPR_BASE_OPCODE = 0x7c0002a6, ATTN_OPCODE = 0x00000200, OPCODE_18 = 18, SELF_SAVE_FUNC_ADD = 0x2300, diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index a2661aaf2..f41086b44 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -54,26 +54,26 @@ namespace stopImageSection const StopSprReg_t g_sprRegister[] = { - { P9_STOP_SPR_CIABR, true, 0 }, - { P9_STOP_SPR_DAWR, true, 1 }, - { P9_STOP_SPR_DAWRX, true, 2 }, - { P9_STOP_SPR_HSPRG0, true, 3 }, - { P9_STOP_SPR_LDBAR, true, 4, }, - { P9_STOP_SPR_LPCR, true, 5 }, - { P9_STOP_SPR_PSSCR, true, 6 }, - { P9_STOP_SPR_MSR, true, 7 }, - { P9_STOP_SPR_HRMOR, false, 20 }, - { P9_STOP_SPR_HID, false, 21 }, - { P9_STOP_SPR_HMEER, false, 22 }, - { P9_STOP_SPR_PMCR, false, 23 }, - { P9_STOP_SPR_PTCR, false, 24 }, - { P9_STOP_SPR_SMFCTRL, true, 28 }, - { P9_STOP_SPR_USPRG0, true, 29 }, - { P9_STOP_SPR_USPRG1, true, 30 }, - { P9_STOP_SPR_URMOR, false, 31 }, + { P9_STOP_SPR_CIABR, true, 0 }, + { P9_STOP_SPR_DAWR, true, 1 }, + { P9_STOP_SPR_DAWRX, true, 2 }, + { P9_STOP_SPR_HSPRG0, true, 3 }, + { P9_STOP_SPR_LDBAR, true, 4, }, + { P9_STOP_SPR_LPCR, true, 5 }, + { P9_STOP_SPR_PSSCR, true, 6 }, + { P9_STOP_SPR_MSR, true, 7 }, + { P9_STOP_SPR_HRMOR, false, 255 }, + { P9_STOP_SPR_HID, false, 21 }, + { P9_STOP_SPR_HMEER, false, 22 }, + { P9_STOP_SPR_PMCR, false, 23 }, + { P9_STOP_SPR_PTCR, false, 24 }, + { P9_STOP_SPR_SMFCTRL, true, 28 }, + { P9_STOP_SPR_USPRG0, true, 29 }, + { P9_STOP_SPR_USPRG1, true, 30 }, + { P9_STOP_SPR_URMOR, false, 255 }, }; -const uint32_t MAX_SPR_SUPPORTED = 17; +const uint32_t MAX_SPR_SUPPORTED = 17; const uint32_t LEGACY_CORE_SCOM_SUPPORTED = 15; const uint32_t LEGACY_QUAD_SCOM_SUPPORTED = 63; @@ -255,7 +255,7 @@ STATIC uint32_t getOriInstruction( const uint16_t i_Rs, const uint16_t i_Ra, */ STATIC uint32_t genKeyForSprLookup( const CpuReg_t i_regId ) { - return getOriInstruction( 0, 0, (uint16_t) i_regId ); + return getOriInstruction( 24, 0, (uint16_t) i_regId ); } //----------------------------------------------------------------------------- @@ -330,7 +330,7 @@ STATIC uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) */ STATIC uint32_t getMfmsrInstruction( const uint16_t i_Rt ) { - uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | (MFMSR_CONST)); + uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | ((MFMSR_CONST)<< 1)); return SWIZZLE_4_BYTE(mfmsrInstOpcode); } @@ -361,14 +361,19 @@ STATIC uint32_t getRldicrInstruction( const uint16_t i_Ra, const uint16_t i_Rs, STATIC uint32_t getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_sprNum ) { - uint32_t mfsprInstOpcode = 0; - mfsprInstOpcode = (( OPCODE_31 << 26 ) | ( i_Rt << 21 ) | ( i_sprNum << 11 ) | ( MFSPR_CONST << 1 )); + uint32_t mfsprInstOpcode = 0; + uint32_t temp = (( i_sprNum & 0x03FF ) << 11); + mfsprInstOpcode = (uint8_t)i_Rt << 21; + mfsprInstOpcode |= (( temp & 0x0000F800 ) << 5); + mfsprInstOpcode |= (( temp & 0x001F0000 ) >> 5); + mfsprInstOpcode |= MFSPR_BASE_OPCODE; + return SWIZZLE_4_BYTE(mfsprInstOpcode); } //----------------------------------------------------------------------------- -STATIC uint32_t getBranchLinkRegInstruction( ) +STATIC uint32_t getBranchLinkRegInstruction(void) { uint32_t branchConstInstOpcode = 0; branchConstInstOpcode = (( OPCODE_18 << 26 ) | ( SELF_SAVE_FUNC_ADD ) | 0x03 ); @@ -455,7 +460,7 @@ STATIC StopReturnCode_t lookUpSprInImage( uint32_t* i_pThreadSectLoc, const uint STATIC StopReturnCode_t updateSprEntryInImage( uint32_t* i_pSprEntryLocation, const CpuReg_t i_regId, const uint64_t i_regData, - const SprEntryUpdateMode i_mode + const enum SprEntryUpdateMode i_mode ) { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; @@ -615,14 +620,14 @@ STATIC StopReturnCode_t getSprRegIndexAdjustment( const uint32_t i_saveMaskPos, do { - if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_19 )) || + if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_20 )) || (( i_saveMaskPos >= SPR_BIT_POS_25 ) && ( i_saveMaskPos <= SPR_BIT_POS_27 )) ) { l_rc = STOP_SAVE_SPR_BIT_POS_RESERVE; break; } - if( (i_saveMaskPos > SPR_BIT_POS_19) && (i_saveMaskPos < SPR_BIT_POS_25 ) ) + if( (i_saveMaskPos > SPR_BIT_POS_20) && (i_saveMaskPos < SPR_BIT_POS_25) ) { *i_sprAdjIndex = 12; } @@ -1332,7 +1337,7 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, * @param[in] i_pSaveSprLoc start location of save entry for a given SPR. * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. */ -StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart, +STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart, uint32_t i_searchLength, uint32_t** i_pSaveSprLoc ) { int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2); @@ -1363,7 +1368,7 @@ StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveSt * @param[in] i_sprNum Id of the SPR for which entry needs to be edited. * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. */ -StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) +STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; @@ -1411,6 +1416,7 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, uint32_t* l_pRestoreStart = NULL; uint32_t* l_pSprSave = NULL; void* l_pTempLoc = NULL; + uint32_t * l_pTempWord = NULL; SmfHomerSection_t* l_pHomer = NULL; uint8_t l_selfRestVer = 0; @@ -1440,6 +1446,11 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, { l_sprPos = g_sprRegister[l_sprIndex].iv_saveMaskPos; + if( l_sprPos > MAX_SPR_BIT_POS ) + { + continue; + } + //Check if a given SPR needs to be self-saved each time on STOP entry if( i_saveRegVector & ( TEST_BIT_PATTERN >> l_sprPos ) ) @@ -1493,6 +1504,19 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, //update specific instructions of self save region to enable saving for SPR l_rc = updateSelfSaveEntry( l_pSprSave, g_sprRegister[l_sprIndex].iv_sprId ); + if( l_rc ) + { + MY_ERR( "Failed to update self save instructions for 0x%08x", + (uint32_t) g_sprRegister[l_sprIndex].iv_sprId ); + } + + if( l_pTempLoc ) + { + l_pTempWord = (uint32_t *)l_pTempLoc; + l_pTempWord++; + *l_pTempWord = getXorInstruction( 0, 0, 0 ); + } + }// end if( i_saveRegVector..) }// end for } diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H index 17caedb3c..ef0d9d1ec 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H @@ -148,7 +148,6 @@ typedef enum BIT_POS_LPCR = 5, BIT_POS_PSSCR = 6, BIT_POS_MSR = 7, - BIT_POS_HRMOR = 20, BIT_POS_HID = 21, BIT_POS_HMEER = 22, BIT_POS_PMCR = 23, @@ -156,7 +155,6 @@ typedef enum BIT_POS_SMFCTRL = 28, BIT_POS_USPRG0 = 29, BIT_POS_USPRG1 = 30, - BIT_POS_URMOR = 31, } SprBitPositionList_t; diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H index 1e9721e01..4e73aab57 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_data_struct.H @@ -67,9 +67,9 @@ enum SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), MAX_THREAD_LEVEL_SPRS = 11, MAX_CORE_LEVEL_SPRS = 6, - MAX_SPR_BIT_POS = 31, + MAX_SPR_BIT_POS = 30, SPR_BIT_POS_8 = 8, - SPR_BIT_POS_19 = 19, + SPR_BIT_POS_20 = 20, SPR_BIT_POS_25 = 25, SPR_BIT_POS_27 = 27, }; diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml index e5dd8a3ab..e6dfaaf33 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml @@ -731,7 +731,8 @@ <!-- *********************************************************************** --> <hwpError> <rc>RC_URMOR_RESTORE_ENTRY_FAILED</rc> - <description>hcode image build procedure failed to create URMOR restore entry</description> + <description>hcode image build procedure failed to create URMOR restore entry. + It is meant for test and debug environment.</description> <ffdc>PIR</ffdc> <ffdc>STOP_API_RC</ffdc> <callout> @@ -740,4 +741,29 @@ </callout> </hwpError> <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SELF_SAVE_API_FAILED</rc> + <description>API call for creating SPR self save entry failed. + It is meant for test and debug environment.</description> + <ffdc>PIR</ffdc> + <ffdc>STOP_API_RC</ffdc> + <ffdc>CORE_POS</ffdc> + <ffdc>THREAD_POS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_BAD_UNSECURE_HOMER_VALUE</rc> + <description>Attribute ATTR_UNSECURE_HOMER_ADDRESS is initialized with bad value. Address + is either not aligned with 2MB boundary or b15 of of address value is not 0</description> + <ffdc>UNSECURE_HOMER_ADDRESS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> </hwpErrors> |