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author | Thi Tran <thi@us.ibm.com> | 2017-07-14 14:44:28 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-10-16 13:56:27 -0400 |
commit | 4b4eded7e95f7548fef9e9b3c097ae202ffe485d (patch) | |
tree | de408b0e658245f2adca5b69fe7fab9c481ec022 /src/import/chips/p9 | |
parent | bd05ce58497010405de900c9ff39cd32f5dc32da (diff) | |
download | talos-hostboot-4b4eded7e95f7548fef9e9b3c097ae202ffe485d.tar.gz talos-hostboot-4b4eded7e95f7548fef9e9b3c097ae202ffe485d.zip |
L3 Update - p9_phb_hv_utils HWP
Change-Id: If1e832307cbb57924be8ef7aaa981a44fb32de2d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43160
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48379
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
3 files changed, 189 insertions, 229 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.C index 3a581df2d..a2a820b56 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.C @@ -22,192 +22,182 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -//----------------------------------------------------------------------------------- -// -// + +///--------------------------------------------------------------------------- +/// /// @file p9_phb_hv_utils.C -/// @brief Functions to access PHB HV register space (FAPI) +/// @brief Functions to access PHB HV register space (FAPI2) /// -// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com -// *HWP FW Owner: Thi Tran thi@us.ibm.com -// *HWP Team: Nest -// *HWP Level: 2 -// *HWP Consumed by: HB -// -//----------------------------------------------------------------------------------- - - -//----------------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------------- -#include <p9_phb_hv_utils.H> -#include "p9_misc_scom_addresses.H" -#include "p9_misc_scom_addresses_fld.H" +/// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com +/// *HWP FW Owner: Thi Tran thi@us.ibm.com +/// *HWP Team: Nest +/// *HWP Level: 3 +/// *HWP Consumed by: FSP +/// +///--------------------------------------------------------------------------- -extern "C" -{ +///--------------------------------------------------------------------------- +/// Includes +///--------------------------------------------------------------------------- +#include <p9_phb_hv_utils.H> +#include <p9_misc_scom_addresses.H> +#include <p9_misc_scom_addresses_fld.H> //--------------------------------------------------------------------------------- // NOTE: description in header //--------------------------------------------------------------------------------- - fapi2::ReturnCode p9_phb_hv_check_etu_state(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target) - { - FAPI_DBG(" Start p9_phb_hv_check_etu_state"); - - fapi2::buffer<uint64_t> l_buf; - - //Read state of ETU Reset Register - FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf)); - FAPI_DBG(" ETU Reset Register %#lx", l_buf()); - - FAPI_ASSERT(!l_buf.getBit<PHB_PHBRESET_REG_PE_ETU_RESET>(), - fapi2::P9_PHB_HV_UTILS_ETU_RESET_ACTIVE() - .set_TARGET(i_target) - .set_ADDRESS(PHB_PHBRESET_REG) - .set_DATA(l_buf), - " ETU is in reset!"); - - - fapi_try_exit: - FAPI_DBG(" Exiting p9_phb_hv_check_etu_state"); - return fapi2::current_err; - } - +fapi2::ReturnCode p9_phb_hv_check_etu_state( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target) +{ + FAPI_DBG(" Start p9_phb_hv_check_etu_state"); + fapi2::buffer<uint64_t> l_buf; + + //Read state of ETU Reset Register + FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf), + "Error from getScom (0x%.16llX)", PHB_PHBRESET_REG); + FAPI_DBG(" ETU Reset Register %#lx", l_buf()); + FAPI_ASSERT(!l_buf.getBit<PHB_PHBRESET_REG_PE_ETU_RESET>(), + fapi2::P9_PHB_HV_UTILS_ETU_RESET_ACTIVE() + .set_TARGET(i_target) + .set_ADDRESS(PHB_PHBRESET_REG) + .set_DATA(l_buf), + " ETU is in reset!"); + +fapi_try_exit: + FAPI_DBG(" Exiting p9_phb_hv_check_etu_state"); + return fapi2::current_err; +} //--------------------------------------------------------------------------------- // NOTE: description in header //--------------------------------------------------------------------------------- - fapi2::ReturnCode p9_phb_hv_check_args(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size) +fapi2::ReturnCode p9_phb_hv_check_args( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size) +{ + FAPI_DBG(" Start p9_phb_hv_check_args"); + uint32_t l_actualTransSize; + + if (i_size) { - FAPI_DBG(" Start p9_phb_hv_check_args"); - - uint32_t l_actualTransSize; - - if (i_size) - { - l_actualTransSize = 4; - } - else - { - l_actualTransSize = 8; - } - - FAPI_DBG(" Addr 0x%04llX, Size 0x%d", i_address, l_actualTransSize); - - //Check the address alignment - FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)), - fapi2::P9_PHB_HV_UTILS_INVALID_ARGS() - .set_TARGET(i_target) - .set_ADDRESS(i_address), - " Address is not aligned"); - - //Make sure the address is within the PHB HV bounds - FAPI_ASSERT(i_address <= PHB_HV_MAX_ADDR, - fapi2::P9_PHB_HV_UTILS_INVALID_ARGS() - .set_TARGET(i_target) - .set_ADDRESS(i_address), - " Address exceeds supported PHB HV address range, 0x0000 - 0x1FFF"); - - - fapi_try_exit: - FAPI_DBG(" Exiting p9_phb_hv_check_args"); - return fapi2::current_err; + l_actualTransSize = 4; + } + else + { + l_actualTransSize = 8; } + FAPI_DBG(" Addr 0x%04llX, Size 0x%d", i_address, l_actualTransSize); + + //Check the address alignment + FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)), + fapi2::P9_PHB_HV_UTILS_INVALID_ARGS() + .set_TARGET(i_target) + .set_ADDRESS(i_address) + .set_SIZE(l_actualTransSize), + "Input address (0x%04llX) is not aligned", i_address); + + //Make sure the address is within the PHB HV bounds + FAPI_ASSERT(i_address <= PHB_HV_MAX_ADDR, + fapi2::P9_PHB_HV_UTILS_INVALID_ARGS() + .set_TARGET(i_target) + .set_ADDRESS(i_address) + .set_SIZE(l_actualTransSize), + "Input addr (0x%04llX) exceeds supported PHB HV address of " + "0x%04llX", i_address, PHB_HV_MAX_ADDR); + +fapi_try_exit: + FAPI_DBG(" Exiting p9_phb_hv_check_args"); + return fapi2::current_err; +} //--------------------------------------------------------------------------------- // NOTE: description in header //--------------------------------------------------------------------------------- - fapi2::ReturnCode p9_phb_hv_setup(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size) - { - FAPI_DBG(" Start p9_phb_hv_setup"); - - fapi2::buffer<uint64_t> phb_hv_addr_reg_data(i_address); - - //Set Valid bit to allow read/write access - phb_hv_addr_reg_data.setBit<PHB_HV_IND_ADDR_VALID_BIT>(); - - //Set Size for 8B or 4B ops - if (i_size) - { - phb_hv_addr_reg_data.setBit<PHB_HV_IND_ADDR_SIZE_BIT>(); - } - +fapi2::ReturnCode p9_phb_hv_setup(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, + bool const i_size) +{ + FAPI_DBG(" Start p9_phb_hv_setup"); + fapi2::buffer<uint64_t> phb_hv_addr_reg_data(i_address); - //This sets everything that should be set for the PHB HV Indirect Address Register - FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data); - FAPI_TRY(fapi2::putScom(i_target, PHB_HV_INDIRECT_ADDR_REG, phb_hv_addr_reg_data), - " Error writing to PHB HV Indirect Address Register"); + //Set Valid bit to allow read/write access + phb_hv_addr_reg_data.setBit<PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VLD>(); - fapi_try_exit: - FAPI_DBG(" Exiting p9_phb_hv_setup"); - return fapi2::current_err; + //Set Size for 8B or 4B ops + if (i_size) + { + phb_hv_addr_reg_data.setBit<PHB_PHB4_SCOM_HVIAR_HV_REQ_4B>(); } + //This sets everything that should be set for the PHB HV Indirect Address Register + FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data); + FAPI_TRY(fapi2::putScom(i_target, PHB_PHB4_SCOM_HVIAR, phb_hv_addr_reg_data), + "Error from putScom (0x%.16llX)", PHB_PHB4_SCOM_HVIAR); + +fapi_try_exit: + FAPI_DBG(" Exiting p9_phb_hv_setup"); + return fapi2::current_err; +} //--------------------------------------------------------------------------------- // NOTE: description in header //--------------------------------------------------------------------------------- - fapi2::ReturnCode p9_phb_hv_write(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size, uint64_t& i_write_data) - { - FAPI_DBG(" Start p9_phb_hv_write"); - - fapi2::buffer<uint64_t> phb_hv_data_reg_data(i_write_data); - - //write the data into the PHB HV Indirect Data Register - FAPI_DBG(" Write Data = 0x%016llX", phb_hv_data_reg_data); - FAPI_TRY(fapi2::putScom(i_target, PHB_HV_INDIRECT_DATA_REG, phb_hv_data_reg_data), - " Error writing to PHB HV Indirect Data Register"); +fapi2::ReturnCode p9_phb_hv_write( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size, uint64_t& i_write_data) +{ + FAPI_DBG(" Start p9_phb_hv_write"); + fapi2::buffer<uint64_t> phb_hv_data_reg_data(i_write_data); + //write the data into the PHB HV Indirect Data Register + FAPI_DBG(" Write Data = 0x%016llX", phb_hv_data_reg_data); + FAPI_TRY(fapi2::putScom(i_target, PHB_PHB4_SCOM_HVIDR, phb_hv_data_reg_data), + "Error from putScom (0x%.16llX)", PHB_PHB4_SCOM_HVIDR); - fapi_try_exit: - FAPI_DBG(" Exiting p9_phb_hv_write"); - return fapi2::current_err; - } +fapi_try_exit: + FAPI_DBG(" Exiting p9_phb_hv_write"); + return fapi2::current_err; +} //--------------------------------------------------------------------------------- // NOTE: description in header //--------------------------------------------------------------------------------- - fapi2::ReturnCode p9_phb_hv_read(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size, uint64_t& o_read_data) - { - FAPI_DBG(" Start p9_phb_hv_read"); - - fapi2::buffer<uint64_t> phb_hv_data_reg_data; - - //Read data from PHB HV Indirect Data Register - FAPI_TRY(fapi2::getScom(i_target, PHB_HV_INDIRECT_DATA_REG, phb_hv_data_reg_data), - " Error writing to PHB HV Indirect Data Register"); - o_read_data = phb_hv_data_reg_data; - FAPI_DBG(" Read Data = 0x%016llX", o_read_data); - +fapi2::ReturnCode p9_phb_hv_read( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size, + uint64_t& o_read_data) +{ + FAPI_DBG(" Start p9_phb_hv_read"); + fapi2::buffer<uint64_t> phb_hv_data_reg_data; - fapi_try_exit: - FAPI_DBG(" Exiting p9_phb_hv_read"); - return fapi2::current_err; - } + //Read data from PHB HV Indirect Data Register + FAPI_TRY(fapi2::getScom(i_target, PHB_PHB4_SCOM_HVIDR, phb_hv_data_reg_data), + "Error from getScom (0x%.16llX)", PHB_PHB4_SCOM_HVIDR); + o_read_data = phb_hv_data_reg_data; + FAPI_DBG(" Read Data = 0x%016llX", o_read_data); +fapi_try_exit: + FAPI_DBG(" Exiting p9_phb_hv_read"); + return fapi2::current_err; +} //--------------------------------------------------------------------------------- // NOTE: description in header //--------------------------------------------------------------------------------- - fapi2::ReturnCode p9_phb_hv_clear(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target) - { - FAPI_DBG(" Start p9_phb_hv_clear"); - - fapi2::buffer<uint64_t> phb_hv_addr_reg_data = 0; - - //Clear the contents of the PHB HV Indirect Address Register - FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data); - FAPI_TRY(fapi2::putScom(i_target, PHB_HV_INDIRECT_ADDR_REG, phb_hv_addr_reg_data), - " Error writing to PHB HV Indirect Address Register"); - - fapi_try_exit: - FAPI_DBG(" Exiting p9_phb_hv_clear"); - return fapi2::current_err; - } - -} // extern "C +fapi2::ReturnCode p9_phb_hv_clear(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target) +{ + FAPI_DBG(" Start p9_phb_hv_clear"); + fapi2::buffer<uint64_t> phb_hv_addr_reg_data = 0; + + //Clear the contents of the PHB HV Indirect Address Register + FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data); + FAPI_TRY(fapi2::putScom(i_target, PHB_PHB4_SCOM_HVIAR, phb_hv_addr_reg_data), + "Error from putScom (0x%.16llX)", PHB_PHB4_SCOM_HVIAR); + +fapi_try_exit: + FAPI_DBG(" Exiting p9_phb_hv_clear"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.H index f60152263..9167bf6ef 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.H @@ -22,74 +22,35 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -//----------------------------------------------------------------------------------- -// *! + +///---------------------------------------------------------------------------- /// @file p9_phb_hv_utils.H -/// @brief Functions to support PHB HV Indirect access procedure (FAPI) +/// @brief Functions to support PHB HV Indirect access procedure (FAPI2) /// -// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com -// *HWP FW Owner: Thi Tran thi@us.ibm.com -// *HWP Team: Nest -// *HWP Level: 2 -// *HWP Consumed by: HB -// ---------------------------------------------------------------------------------- -// *! ADDITIONAL COMMENTS : -// *! -// *! -//----------------------------------------------------------------------------------- - +/// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com +/// *HWP FW Owner: Thi Tran thi@us.ibm.com +/// *HWP Team: Nest +/// *HWP Level: 3 +/// *HWP Consumed by: FSP +/// --------------------------------------------------------------------------- #ifndef _P9_PHB_HV_UTILS_H_ #define _P9_PHB_HV_UTILS_H_ - //----------------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------------- - #include <fapi2.H> //----------------------------------------------------------------------------------- -// Structure definitions -//----------------------------------------------------------------------------------- - -//function pointer typedef definition for HWP call support -typedef fapi2::ReturnCode (*p9_phb_hv_check_etu_state_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&); - -typedef fapi2::ReturnCode (*p9_phb_hv_check_args_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&, const uint32_t, - bool const); - -typedef fapi2::ReturnCode (*p9_phb_hv_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&, const uint32_t, - bool const); - -typedef fapi2::ReturnCode (*p9_phb_hv_write_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&, const uint32_t, - bool const, uint64_t&); - -typedef fapi2::ReturnCode (*p9_phb_hv_read_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&, const uint32_t, - bool const, uint64_t&); - -typedef fapi2::ReturnCode (*p9_phb_hv_clear_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&); - -//----------------------------------------------------------------------------------- // Constant definitions //----------------------------------------------------------------------------------- -//PHB HV Indirect Address & Data Register BAR -const uint32_t PHB_HV_INDIRECT_ADDR_REG = 0x0D010900; -const uint32_t PHB_HV_INDIRECT_DATA_REG = 0x0D010901; - //PHB HV Registers const uint32_t PHB_CORE_RESET_REGISTER = 0x1A10; -//PHB HV Register field/bit definition +//PHB PHB_CORE_RESET_REGISTER field/bit definition const uint32_t PHB_HP_PERST_BIT = 3; -//PHB HV Indirect Address Register field/bit definitions -const uint32_t PHB_HV_IND_ADDR_VALID_BIT = 0; -const uint32_t PHB_HV_IND_ADDR_SIZE_BIT = 1; -const uint32_t PHB_HV_IND_ADDR_AUTO_INC_BIT = 2; -const uint32_t PHB_HV_IND_ADDR_ADDRESS_START_BIT = 51; -const uint32_t PHB_HV_IND_ADDR_ADDRESS_NUM_OF_BITS = 11; - //8B for PHB register access. 4B for Config Ops const uint32_t PHB_HV_IND_ADDR_SIZE_8 = 0; const uint32_t PHB_HV_IND_ADDR_SIZE_4 = 1; @@ -97,9 +58,6 @@ const uint32_t PHB_HV_IND_ADDR_SIZE_4 = 1; //PHB HV address range definition const uint32_t PHB_HV_MAX_ADDR = 0x1FFF; - -extern "C" { - //----------------------------------------------------------------------------------- // Function prototypes //----------------------------------------------------------------------------------- @@ -107,48 +65,59 @@ extern "C" { /// @brief check that the ETU is out of reset for PHB HV accesses /// @param[in] i_target => reference for PHB target /// @return FAPI_RC_SUCCESS if arguments are valid - fapi2::ReturnCode p9_phb_hv_check_etu_state(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target); +fapi2::ReturnCode p9_phb_hv_check_etu_state( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target); -/// @brief does the setup for the PHB HV Indirect operation -/// @brief check that the address is aligned and within the address range allowed by the PHB HV Indirect Address logic +/// @brief check that the address is aligned and within the address range +/// allowed by the PHB HV Indirect Address logic /// @param[in] i_target => reference for PHB target /// @param[in] i_address => address for the PHB HV Indirect operation +/// @param[in] i_size => boolean flag to set the size (true: 4B; false: 8B) /// @return FAPI_RC_SUCCESS if arguments are valid - fapi2::ReturnCode p9_phb_hv_check_args(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size); +fapi2::ReturnCode p9_phb_hv_check_args( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size); /// @brief does the setup for the PHB HV Indirect operation /// @param[in] i_target => reference for PHB target /// @param[in] i_address => address for the PHB HV Indirect operation -/// @param[in] i_size => boolean flag to set the size for 4B or 8B +/// @param[in] i_size => boolean flag to set the size (true: 4B; false: 8B) /// @return FAPI_RC_SUCCESS if setting up the phb_hv registers is a success - fapi2::ReturnCode p9_phb_hv_setup(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size); +fapi2::ReturnCode p9_phb_hv_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size); /// @brief does the write for the PHB HV -/// @param[in] i_target => reference for PHB target -/// @param[in] i_address => address for this write -/// @param[in] i_size => boolean flag to set the size for 4B or 8B -/// @param[in] i_write_data => the data that is to be written to the PHB HV Indirect Data Register +/// @param[in] i_target => reference for PHB target +/// @param[in] i_address => address for this write +/// @param[in] i_size => boolean flag to set the size (true: 4B; false: 8B) +/// @param[in] i_write_data => the data that is to be written to the +/// PHB HV Indirect Data Register /// @return FAPI_RC_SUCCESS if writing the PHB HV is a success - fapi2::ReturnCode p9_phb_hv_write(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size, uint64_t& i_write_data); +fapi2::ReturnCode p9_phb_hv_write( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size, + uint64_t& i_write_data); /// @brief does the read for the PHB HV -/// @param[in] i_target => reference for PHB target -/// @param[in] i_address => address for this read -/// @param[in] i_size => boolean flag to set the size for 4B or 8B +/// @param[in] i_target => reference for PHB target +/// @param[in] i_address => address for this read +/// @param[in] i_size => boolean flag to set the size for 4B or 8B /// @param[out] o_read_data => the data that is read from the PHB HV /// @return FAPI_RC_SUCCESS if reading the PHB HV is a success - fapi2::ReturnCode p9_phb_hv_read(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address, - bool const i_size, uint64_t& o_read_data); +fapi2::ReturnCode p9_phb_hv_read( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, + const uint32_t i_address, + bool const i_size, + uint64_t& o_read_data); /// @brief does the clear for the PHB HV /// @param[in] i_target => reference for PHB target -/// @return FAPI_RC_SUCCESS if reading the PHB HV is a success - fapi2::ReturnCode p9_phb_hv_clear(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target); - - -} // extern "C" +/// @return FAPI_RC_SUCCESS if clearing the PHB HV is a success +fapi2::ReturnCode p9_phb_hv_clear( + const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target); #endif //_P9_PHB_HV_UTILS_H_ diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_phb_hv_utils_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_phb_hv_utils_errors.xml index 1e5f80097..82fc2cc51 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_phb_hv_utils_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_phb_hv_utils_errors.xml @@ -36,7 +36,7 @@ <!-- Add procedure callout --> <callout> <procedure>CODE</procedure> - <priority>LOW</priority> + <priority>HIGH</priority> </callout> </hwpError> <!-- ********************************************************************* --> @@ -47,10 +47,11 @@ </description> <ffdc>TARGET</ffdc> <ffdc>ADDRESS</ffdc> + <ffdc>SIZE</ffdc> <!-- Add procedure callout --> <callout> <procedure>CODE</procedure> - <priority>LOW</priority> + <priority>HIGH</priority> </callout> </hwpError> <!-- ********************************************************************* --> |