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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-06-08 14:42:03 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-06-14 10:56:36 -0400 |
| commit | 4a43554124f7d5c8d14988eeb9cd0dfd4f48dc18 (patch) | |
| tree | 822518305c3bcc4057d68a22929a063d187a445a /src/import/chips/p9 | |
| parent | e2ade14ecc5ee69edacb77408b785472d1368721 (diff) | |
| download | talos-hostboot-4a43554124f7d5c8d14988eeb9cd0dfd4f48dc18.tar.gz talos-hostboot-4a43554124f7d5c8d14988eeb9cd0dfd4f48dc18.zip | |
p9_sbe_common -- mark TP LFIR bit 37 as recoverable
TP LFIR 37 is meant to be marked recoverable for Cumulus
60118 unmasked the bit, but the default action register settings
are programmed to trigger a checkstop. This adjust the action1 register
default to recoverable.
Change-Id: I8d07fdac8eb060ba10929133fdbe93621b8b53e7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60244
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60262
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index 90ca2db6f..f4b8fb467 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -76,7 +76,7 @@ const uint64_t PERV_LFIR_ACTION0[15] = const uint64_t PERV_LFIR_ACTION1[15] = { - 0xF0003C2003800000ULL, // TP + 0xF0003C2007800000ULL, // TP 0xF000000000000000ULL, // N0 0xF000000000000000ULL, // N1 0xF000000000000000ULL, // N2 |
