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| author | Nick Klazynski <jklazyns@us.ibm.com> | 2018-06-19 08:23:37 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-06-21 16:25:00 -0400 |
| commit | 443609a242752db24d1a76b8c54bbb1a54465bc1 (patch) | |
| tree | abf82cb223f64bd702ace4001a5fd2bf814f4fd1 /src/import/chips/p9 | |
| parent | bfebff1e8079b04f649c719fd243ece038e94bcf (diff) | |
| download | talos-hostboot-443609a242752db24d1a76b8c54bbb1a54465bc1.tar.gz talos-hostboot-443609a242752db24d1a76b8c54bbb1a54465bc1.zip | |
Add RL0/RL1 support for CDD1.2
Change-Id: I21d861481b9909ea024934e8b5830521d407c9a7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60873
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60886
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 39 |
1 files changed, 31 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 912234305..856aa2972 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -240,11 +240,10 @@ </attribute> <!-- ********************************************************************* --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_HW430733</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <id>ATTR_CHIP_EC_FEATURE_FLUSH_L1D_TRIG</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> - Nimbus DD2.2 - MTTRIG2 setup to flush L1D - - Always obey SW branch hint bits + MTTRIG2 setup to flush L1D </description> <chipEcFeature> <chip> @@ -254,6 +253,13 @@ <test>EQUAL</test> </ec> </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x12</value> + <test>EQUAL</test> + </ec> + </chip> </chipEcFeature> </attribute> <!-- ********************************************************************* --> @@ -4658,10 +4664,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_CDD11_SEC_MEM</id> + <id>ATTR_CHIP_EC_FEATURE_CORE_CDD11_SECURITY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - Secure memory setting for Cumulus DD1.1 + Security settings for Cumulus DD1.1 </description> <chipEcFeature> <chip> @@ -4675,10 +4681,27 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_CDD11_CDD12_SEC_MEM</id> + <id>ATTR_CHIP_EC_FEATURE_CORE_CDD12_SECURITY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Security settings for Cumulus DD1.2 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x12</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_CORE_CDD11_CDD12_SECURITY</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> - Secure memory setting for Cumulus DD1.1 and DD1.2 + Security settings for Cumulus DD1.1 and DD1.2 </description> <chipEcFeature> <chip> |
