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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-06-05 12:41:06 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-06-22 14:51:06 -0400 |
| commit | 36839984fe01eee7726d7dc81d89814786c87b99 (patch) | |
| tree | 9704025f32a08a9e9e7ef50faba6a3ca1e9f6ba7 /src/import/chips/p9 | |
| parent | 4696c5090436390121826110fe280b988c2677c7 (diff) | |
| download | talos-hostboot-36839984fe01eee7726d7dc81d89814786c87b99.tar.gz talos-hostboot-36839984fe01eee7726d7dc81d89814786c87b99.zip | |
p9_throttle_sync -- clear refresh sync type after issuing IPL sync
Refresh sync is desired at IPL time, but not needed at runtime as
OCC programs throttles. This change simply clears the refresh
sync type after issuing the IPL sync.
Change-Id: I7a4ac00891a179940a62d9d7eb7450734364cd5d
CQ: SW432160
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59971
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59993
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C index e86021ea4..e62ff6ab1 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,7 +49,8 @@ ///---------------------------------------------------------------------------- /// Constant definitions ///---------------------------------------------------------------------------- -const uint8_t SUPER_SYNC_BIT = 14; +const uint8_t MBA_REFRESH_SYNC_BIT = 8; +const uint8_t SUPER_SYNC_BIT = 14; const uint8_t MAX_MC_SIDES_PER_PROC = 2; // MC01, MC23 const uint8_t MAX_MC_PER_PROC = 4; // MC0, MC1, MC2, MC3 const uint8_t MAX_MC_PER_SIDE = 2; // MC0, MC1 or MC2, MC3 @@ -272,7 +273,7 @@ fapi2::ReturnCode progMaster(const fapi2::Target<T>& i_mcTarget) // SUPER_SYNC_BIT == bit 14, supersync for Nimbus, reserved for cumulus. // Clear it in both cases. l_scomData.setBit<MCS_MCSYNC_SYNC_TYPE, - MCS_MCSYNC_SYNC_TYPE_LEN>().clearBit(SUPER_SYNC_BIT); + MCS_MCSYNC_SYNC_TYPE_LEN>().clearBit<SUPER_SYNC_BIT>(); l_scomMask.setBit<MCS_MCSYNC_SYNC_TYPE, MCS_MCSYNC_SYNC_TYPE_LEN>(); @@ -294,6 +295,19 @@ fapi2::ReturnCode progMaster(const fapi2::Target<T>& i_mcTarget) // Note: No need to read Sync replay count and retry in P9. + // -------------------------------------------------------------- + // 4. Clear refresh sync bit + // -------------------------------------------------------------- + l_scomData.flush<0>(); + l_scomMask.flush<0>().setBit<MBA_REFRESH_SYNC_BIT>(); + + FAPI_INF("Writing MCS_MCSYNC reg 0x%.16llX: Mask 0x%.16llX , Data 0x%.16llX", + MCS_MCSYNC, l_scomMask, l_scomData); + FAPI_TRY(fapi2::putScomUnderMask(i_mcTarget, MCS_MCSYNC, + l_scomData, l_scomMask), + "putScomUnderMask() returns an error (Sync), MCS_MCSYNC reg 0x%.16llX", + MCS_MCSYNC); + fapi_try_exit: FAPI_DBG("Exiting progMaster"); return fapi2::current_err; |
