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| author | Nick Bofferding <bofferdn@us.ibm.com> | 2018-06-05 13:06:57 -0500 |
|---|---|---|
| committer | Nicholas E. Bofferding <bofferdn@us.ibm.com> | 2018-06-05 23:56:26 -0400 |
| commit | 1db54dcc27d4061114c9466ec5fb72121420c5eb (patch) | |
| tree | 4539f1e56ce2dfdfc39ea09820787dadeb49ee0f /src/import/chips/p9 | |
| parent | fe439a0d9ef0830377b69e0db7e205df582cf374 (diff) | |
| download | talos-hostboot-1db54dcc27d4061114c9466ec5fb72121420c5eb.tar.gz talos-hostboot-1db54dcc27d4061114c9466ec5fb72121420c5eb.zip | |
Secure Boot: Disable cache of 2010800 Centaur register
Disabling caching of the 2010800 MBI Fault Isolation Register on Centaur
since the HW can flip on bits asynchronously in a way that cache code cannot
handle
Change-Id: I61554e01089043c1417e78bb7aac25f041a1a441
CQ: SW432157
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59977
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/security/Centaur_Register_List.csv | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/src/import/chips/p9/security/Centaur_Register_List.csv b/src/import/chips/p9/security/Centaur_Register_List.csv index 630913628..e57240dd1 100644 --- a/src/import/chips/p9/security/Centaur_Register_List.csv +++ b/src/import/chips/p9/security/Centaur_Register_List.csv @@ -1,9 +1,11 @@ #Register Address,WAND,WOR,Init/Expected Value,Mask Value, 1000000,1000004,1000005,7001900000000003,, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # Some bits (see mask) are not tracking as expected 2000000,2000004,2000005,7001900000000003,FFFE7FFFFFFFFFFD, -2010800,2010801,2010802,0000400000000000,, +# @TODO: CQ SW431769 +# This is a FIR register and bits randomly pop on, making caching unreliable +#2010800,2010801,2010802,0000400000000000,, 2010803,2010804,2010805,FFFFFFE000000000,, 2010C42,,,,, 201140A,,,,, @@ -36,28 +38,28 @@ 2012300,,,0000A00000000000,, 201230B,,,,, 2030000,,,,, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # 0:1 CLOCK_CMD masked off because it auto-resets to 0 # Right now mask those bits off for the comparison, but consider # modeling the auto reset behavior 2030006,,,0FE00E0000000000,3FFFFFFFFFFFFFFF, 2030007,,,,, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # Enabling causes 2011882 to report wrongly for some reason #20F0012,20F0013,20F0014,4016620000000000,3FFFBDFFFFFFFFFF, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # This is broken, needs more attention #3000000,3000004,3000005,7001900000000003,, 3010414,,,7FFFFFFFFFFFD7FF,, 3010415,,,BFFFFFFFFFFFEFFF,, 3010433,,,8484212100000000,, 301060A,,,,, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # First 2 bits reset by HW without SW knowledge # So need to either let the HW read through for these bits, or # ignore the register #301060B,,,,3FFFFFFFFFFFFFFF, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # Expected value is way off from actual value for # unknown reasons. Fix or ignore the register #301060D,,,,, @@ -117,7 +119,7 @@ 3010651,,,,, 3010652,,,,, 3010653,,,,, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # First 2 bits reset by HW without SW knowledge # So need to either let the HW read through for these bits, or # ignore the register @@ -137,7 +139,7 @@ 3012300,,,0000A00000000000,, 301230B,,,,, 3030000,,,,, -# @TODO: RTC 187288 +# @TODO: CQ SW431769 # Enabling this register causes failing # behavior for 303000 #30F0012,30F0013,30F0014,,, |
