diff options
| author | Nick Klazynski <jklazyns@us.ibm.com> | 2018-02-12 09:51:00 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-02-18 13:06:48 -0500 |
| commit | 1c8193dd9e8206daaef01c72d52cb83afed1ae3d (patch) | |
| tree | 91e729b2a8b00362ab4da967d6443c8dd98e02c3 /src/import/chips/p9 | |
| parent | f28cb333bfe398ac9fd6bb89243d62766c0a279f (diff) | |
| download | talos-hostboot-1c8193dd9e8206daaef01c72d52cb83afed1ae3d.tar.gz talos-hostboot-1c8193dd9e8206daaef01c72d52cb83afed1ae3d.zip | |
Enable mixed core xlate; Enable xlate protection feature; Disable LSU clockgate
Change-Id: I1fbc2c79330520d6033adfafe85a89fc71ed3fb0
CQ: HW437820
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53911
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53918
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 520df0bbe..b730c7935 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -3317,6 +3317,78 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_PREVENT_Q0_HV_ACCESS</id>> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> + <description> + Enable feature, preventing access to quadrant 0 in hypervisor mode when LPIDR != 0 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x22</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x11</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_MIXED_CORE_XLATE</id>> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> + <description> + Enable mixed core (HPT/Radix) translation + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x22</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x11</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW437820</id>> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> + <description> + HW437820 - LSU clockgating issue + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x22</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x11</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW407165</id>> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> |
