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| author | Stephen Glancy <sglancy@us.ibm.com> | 2016-08-17 11:19:10 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-08-22 13:51:35 -0400 |
| commit | 19eb5718ee472094163e55b4f02cc3d019ae2215 (patch) | |
| tree | 2cbfcac3ce1688ed7a82221042bf7b8ba6bca447 /src/import/chips/p9 | |
| parent | 4cb8fb9c949f37cad8a4225014891c42a92351e7 (diff) | |
| download | talos-hostboot-19eb5718ee472094163e55b4f02cc3d019ae2215.tar.gz talos-hostboot-19eb5718ee472094163e55b4f02cc3d019ae2215.zip | |
Fixed eff_config attr generation
Attributes generation fixed:
read_preamble_train
odt_input_buffer
Change-Id: Ib23f2164dfee9386fa521e541b9baeb6cf5d39e1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28405
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28409
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
4 files changed, 13 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index dec791a4e..01f6cf413 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -61,7 +61,7 @@ mrs04_data::mrs04_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_vref_mon(0), iv_cs_cmd_latency(0), iv_ref_abort(0), - iv_rd_pre_train_mode(0), + iv_rd_pre_train_mode(fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE), iv_rd_preamble(0), iv_wr_preamble(0), iv_ppr(0) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index 5a6f963d6..74acd2116 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -58,7 +58,7 @@ mrs05_data::mrs05_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, iv_ca_parity_latency(0), iv_crc_error_clear(0), iv_ca_parity_error_status(0), - iv_odt_input_buffer(0), + iv_odt_input_buffer(fapi2::ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED), iv_ca_parity(0), iv_data_mask(0), iv_write_dbi(0), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index f3bbdaf84..f5c078782 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -2037,7 +2037,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::odt_input_buffer(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM + // keeping this value as 0x01, given that we know that that works in sim + constexpr uint8_t SIM_VALUE = 0x01; std::vector<uint8_t> l_attrs_odt_input_buffer(PORTS_PER_MCS, 0); // Targets @@ -2047,9 +2048,15 @@ fapi2::ReturnCode eff_config::odt_input_buffer(const fapi2::Target<TARGET_TYPE_D // Current index const auto l_port_num = index(l_mca); + //keep simulation to values we know work + uint8_t is_sim = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim) ); + + FAPI_TRY( eff_odt_input_buff(l_mcs, l_attrs_odt_input_buffer.data()) ); - l_attrs_odt_input_buffer[l_port_num] = 0x01; + //sim vs actual hardware value + l_attrs_odt_input_buffer[l_port_num] = is_sim ? SIM_VALUE : fapi2::ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_ODT_INPUT_BUFF, l_mcs, @@ -2176,14 +2183,13 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::read_preamble_train(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) ); std::vector<uint8_t> l_attrs_rd_preamble_train(PORTS_PER_MCS, 0); FAPI_TRY( eff_rd_preamble_train(l_mcs, l_attrs_rd_preamble_train.data()) ); - l_attrs_rd_preamble_train[l_port_num] = 0x00; + l_attrs_rd_preamble_train[l_port_num] = fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_RD_PREAMBLE_TRAIN, l_mcs, diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 518f64bd8..f8201b834 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1802,7 +1802,7 @@ </description> <initToZero></initToZero> <valueType>uint8</valueType> - <enum>DEACTIVATED = 0, ACTIVATED = 1</enum> + <enum>ACTIVATED = 0, DEACTIVATED = 1</enum> <writeable/> <array>2</array> <mssAccessorName>eff_odt_input_buff</mssAccessorName> |
