Expanding MCU tag fifo settings to be freq dependent.

Change-Id: I46baeb1bb6f076c132e735724b094ee8a99e9257
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44917
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46019
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>

4 files changed, 334 insertions, 10 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C
index d005847f6..188f46cde 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C
@@ -29,14 +29,23 @@
 
 using namespace fapi2;
 
+constexpr uint64_t literal_0 = 0;
+constexpr uint64_t literal_1 = 1;
+constexpr uint64_t literal_1167 = 1167;
+constexpr uint64_t literal_1000 = 1000;
+constexpr uint64_t literal_1273 = 1273;
+constexpr uint64_t literal_1200 = 1200;
+constexpr uint64_t literal_1400 = 1400;
+constexpr uint64_t literal_1500 = 1500;
+constexpr uint64_t literal_0b01 = 0b01;
+constexpr uint64_t literal_5 = 5;
+constexpr uint64_t literal_7 = 7;
 constexpr uint64_t literal_4 = 4;
 constexpr uint64_t literal_8 = 8;
-constexpr uint64_t literal_1 = 1;
 constexpr uint64_t literal_24 = 24;
 constexpr uint64_t literal_12 = 12;
 constexpr uint64_t literal_0b0100 = 0b0100;
 constexpr uint64_t literal_28 = 28;
-constexpr uint64_t literal_0 = 0;
 constexpr uint64_t literal_0x1 = 0x1;
 constexpr uint64_t literal_0x3 = 0x3;
 constexpr uint64_t literal_0x5 = 0x5;
@@ -49,6 +58,7 @@ constexpr uint64_t literal_0x33 = 0x33;
 constexpr uint64_t literal_0x40 = 0x40;
 constexpr uint64_t literal_3 = 3;
 constexpr uint64_t literal_0b0 = 0b0;
+constexpr uint64_t literal_2 = 2;
 
 fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0,
                                const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT3)
@@ -58,6 +68,18 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0
         fapi2::ATTR_NAME_Type l_chip_id;
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT3, l_chip_id));
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT3, l_chip_ec));
+        fapi2::ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC_Type l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC, TGT3,
+                               l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC));
+        fapi2::ATTR_MC_SYNC_MODE_Type l_TGT3_ATTR_MC_SYNC_MODE;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, TGT3, l_TGT3_ATTR_MC_SYNC_MODE));
+        fapi2::ATTR_FREQ_PB_MHZ_Type l_TGT1_ATTR_FREQ_PB_MHZ;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, TGT1, l_TGT1_ATTR_FREQ_PB_MHZ));
+        fapi2::ATTR_FREQ_MCA_MHZ_Type l_TGT1_ATTR_FREQ_MCA_MHZ;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_MCA_MHZ, TGT1, l_TGT1_ATTR_FREQ_MCA_MHZ));
+        uint64_t l_def_MCA_FREQ = l_TGT1_ATTR_FREQ_MCA_MHZ;
+        uint64_t l_def_MN_FREQ_RATIO = ((literal_1000 * l_def_MCA_FREQ) / l_TGT1_ATTR_FREQ_PB_MHZ);
+        uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1;
         uint64_t l_def_ENABLE_AMO_CACHING = literal_1;
         uint64_t l_def_ENABLE_AMO_CLEAN_LINES = literal_1;
         uint64_t l_def_ENABLE_DYNAMIC_64_128B_READS = literal_0;
@@ -74,10 +96,110 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2));
         uint64_t l_def_MC_EPSILON_CFG_T2 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 + literal_6) / literal_4);
         uint64_t l_def_ENABLE_MCBUSY = literal_1;
-        uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1;
         uint64_t l_def_MCICFG_REPLAY_DELAY = literal_1;
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x5010811ull, l_scom_buffer ));
+
+            if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_1) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_0)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_ON = 0x1;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_ON );
+            }
+            else if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_1) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF = 0x0;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF );
+            }
+            else if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO < literal_1167)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF = 0x0;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1200))
+                      && (l_def_MN_FREQ_RATIO < literal_1273)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF = 0x0;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1167))
+                      && (l_def_MN_FREQ_RATIO < literal_1200)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF = 0x0;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1273))
+                      && (l_def_MN_FREQ_RATIO < literal_1400)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF = 0x0;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1400))
+                      && (l_def_MN_FREQ_RATIO < literal_1500)))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF = 0x0;
+                l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ASYNC_MODE_OFF );
+            }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x5010811ull, l_scom_buffer));
+        }
+        {
+            FAPI_TRY(fapi2::getScom( TGT0, 0x501081bull, l_scom_buffer ));
+
+            constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_SELECT_LOCAL_HANG_PULSE_OFF = 0x0;
+            l_scom_buffer.insert<1, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_SELECT_LOCAL_HANG_PULSE_OFF );
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_SELECT_PB_HANG_PULSE_ON = 0x1;
+                l_scom_buffer.insert<0, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_SELECT_PB_HANG_PULSE_ON );
+            }
+
+            l_scom_buffer.insert<2, 2, 62, uint64_t>(literal_0b01 );
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_DISABLE_HARDWARE_TRACE_MANAGER_HANG_ON = 0x1;
+                l_scom_buffer.insert<36, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_DISABLE_HARDWARE_TRACE_MANAGER_HANG_ON );
+            }
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_NONMIRROR_HANG_ON = 0x1;
+                l_scom_buffer.insert<32, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_NONMIRROR_HANG_ON );
+            }
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_MIRROR_HANG_ON = 0x1;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_MIRROR_HANG_ON );
+            }
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_APO_HANG_ON = 0x1;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_APO_HANG_ON );
+            }
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                constexpr auto l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_CLIB_HANG_ON = 0x1;
+                l_scom_buffer.insert<35, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCTO_ENABLE_CLIB_HANG_ON );
+            }
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                l_scom_buffer.insert<37, 3, 61, uint64_t>(literal_5 );
+            }
+
+            if ((l_def_ENABLE_MCU_TIMEOUTS == literal_1))
+            {
+                l_scom_buffer.insert<5, 3, 61, uint64_t>(literal_7 );
+            }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x501081bull, l_scom_buffer));
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5010823ull, l_scom_buffer ));
 
             l_scom_buffer.insert<4, 4, 60, uint64_t>(literal_4 );
@@ -272,8 +394,42 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x701090eull, l_scom_buffer ));
 
-            constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF = 0x0;
-            l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF );
+            if ((l_TGT3_ATTR_MC_SYNC_MODE == literal_1))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF = 0x0;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO < literal_1167))
+                      && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_ON = 0x1;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_ON );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1200))
+                      && (l_def_MN_FREQ_RATIO < literal_1273)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_ON = 0x1;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_ON );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1167))
+                      && (l_def_MN_FREQ_RATIO < literal_1200)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_ON = 0x1;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_ON );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1273))
+                      && (l_def_MN_FREQ_RATIO < literal_1400)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF = 0x0;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1400))
+                      && (l_def_MN_FREQ_RATIO < literal_1500)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF = 0x0;
+                l_scom_buffer.insert<33, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MCICFG1Q_ECC_RDC_CFG_FIFO_TENURE_3_OFF );
+            }
+
             l_scom_buffer.insert<4, 1, 63, uint64_t>(literal_0b0 );
             l_scom_buffer.insert<5, 1, 63, uint64_t>(literal_0b0 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x701090eull, l_scom_buffer));
@@ -281,11 +437,116 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target<fapi2::TARGET_TYPE_DMI>& TGT0
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x7010914ull, l_scom_buffer ));
 
-            constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_ON = 0x1;
-            l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_ON );
-            l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_0 );
-            constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
-            l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF );
+            if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_1) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_0)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_ON = 0x1;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_ON );
+            }
+            else if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_1) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF );
+            }
+            else if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO < literal_1167)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1200))
+                      && (l_def_MN_FREQ_RATIO < literal_1273)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1167))
+                      && (l_def_MN_FREQ_RATIO < literal_1200)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_ON = 0x1;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_ON );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1273))
+                      && (l_def_MN_FREQ_RATIO < literal_1400)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1400))
+                      && (l_def_MN_FREQ_RATIO < literal_1500)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0;
+                l_scom_buffer.insert<37, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_NONBYPASS_OFF );
+            }
+
+            if ((l_TGT3_ATTR_MC_SYNC_MODE == literal_1))
+            {
+                l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_0 );
+            }
+            else if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO < literal_1167)))
+            {
+                l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_0 );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1200))
+                      && (l_def_MN_FREQ_RATIO < literal_1273)))
+            {
+                l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_0 );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1167))
+                      && (l_def_MN_FREQ_RATIO < literal_1200)))
+            {
+                l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_0 );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1273))
+                      && (l_def_MN_FREQ_RATIO < literal_1400)))
+            {
+                l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_1 );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1400))
+                      && (l_def_MN_FREQ_RATIO < literal_1500)))
+            {
+                l_scom_buffer.insert<35, 2, 62, uint64_t>(literal_2 );
+            }
+
+            if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_1) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_0)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF );
+            }
+            else if (((l_TGT3_ATTR_MC_SYNC_MODE == literal_1) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_ON = 0x1;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_ON );
+            }
+            else if ((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO < literal_1167))
+                      && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_ON = 0x1;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_ON );
+            }
+            else if (((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1200))
+                       && (l_def_MN_FREQ_RATIO < literal_1273)) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF );
+            }
+            else if (((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1167))
+                       && (l_def_MN_FREQ_RATIO < literal_1200)) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF );
+            }
+            else if (((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1273))
+                       && (l_def_MN_FREQ_RATIO < literal_1400)) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF );
+            }
+            else if (((((l_TGT3_ATTR_MC_SYNC_MODE == literal_0) && (l_def_MN_FREQ_RATIO >= literal_1400))
+                       && (l_def_MN_FREQ_RATIO < literal_1500)) && (l_TGT3_ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC == literal_1)))
+            {
+                constexpr auto l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF = 0x0;
+                l_scom_buffer.insert<34, 1, 63, uint64_t>(l_MCP_CHAN0_CHI_MBSECCQ_DELAY_VALID_1X_OFF );
+            }
+
             FAPI_TRY(fapi2::putScom(TGT0, 0x7010914ull, l_scom_buffer));
         }
         {
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 232d8fd7b..e589963df 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -27766,6 +27766,30 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief ATTR_FREQ_MCA_MHZ getter
+/// @param[out] uint32_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  The frequency of the memory controller channel. In synchronous mode, this is
+/// equivalent to ATTR_FREQ_PB_MHZ. This may be independently set per pair of memory
+/// channels if operating in asynchronous mode, but this configuration is not
+/// anticipated. This clock drives the MCU queues, and all the associated logic that
+/// drives the inputs to the DMI and reads its
+/// outputs.
+///
+inline fapi2::ReturnCode freq_mca_mhz(uint32_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_MCA_MHZ, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_FREQ_MCA_MHZ: 0x%lx (system target)",
+             uint64_t(fapi2::current_err));
+    return fapi2::current_err;
+}
+
 
 }
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 61e50fda6..556f03dc4 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -4653,6 +4653,24 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW413362_P9UDD11_ASYNC</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Program MCA ECC logic to support Cumulus DD1.1
+      asynchronus boundary crossing requirements
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CUMULUS</name>
+        <ec>
+          <value>0x11</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK</id>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index f456c8464..a67e37b94 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -47,6 +47,27 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
+  <id>ATTR_FREQ_MCA_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The frequency of the memory controller channel. In synchronous mode,
+    this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set
+    per pair of memory channels if operating in asynchronous mode,
+    but this configuration is not anticipated. This clock drives the MCU queues,
+    and all the associated logic that drives the inputs to the DMI and reads
+    its outputs.
+  </description>
+  <valueType>uint32</valueType>
+  <enum>
+    2000 = 2000,
+    2400 = 2400
+  </enum>
+  <writeable/>
+  <platInit/>
+  <mssAccessorName>freq_mca_mhz</mssAccessorName>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
   <id>ATTR_FREQ_O_MHZ</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>