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| author | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-01-22 07:24:01 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-02-22 11:37:32 -0600 |
| commit | 94af99101a98561e8b16edb11f4ff07126ff5b62 (patch) | |
| tree | 38adbf3d8c1880daa0fbb1cc1bab17991e8bec76 /src/import/chips/p9/xip | |
| parent | 28c943d1fbc23645dc3275e03c5c1654d37b01ba (diff) | |
| download | talos-hostboot-94af99101a98561e8b16edb11f4ff07126ff5b62.tar.gz talos-hostboot-94af99101a98561e8b16edb11f4ff07126ff5b62.zip | |
Header field update for loader
Most of ppe loader need support for slow loader(L1), fast
loader(L2) and pk kernel entry points. Add this information in
XIP header.
Change-Id: I0fd9b58b01431692b1281a3270bb82db814faebe
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23525
Tested-by: Jenkins Server
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24283
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/xip')
| -rw-r--r-- | src/import/chips/p9/xip/p9_xip_image.c | 5 | ||||
| -rw-r--r-- | src/import/chips/p9/xip/p9_xip_image.h | 15 |
2 files changed, 12 insertions, 8 deletions
diff --git a/src/import/chips/p9/xip/p9_xip_image.c b/src/import/chips/p9/xip/p9_xip_image.c index d96c8ae07..e47987be2 100644 --- a/src/import/chips/p9/xip/p9_xip_image.c +++ b/src/import/chips/p9/xip/p9_xip_image.c @@ -1452,7 +1452,6 @@ xipHeaderFind(void* i_image, const char* i_id, P9XipItem* o_item) { HEADER_TOC(magic, iv_magic, P9_XIP_UINT64), - HEADER_TOC(entry_offset, iv_entryOffset, P9_XIP_UINT64), HEADER_TOC(link_address, iv_linkAddress, P9_XIP_UINT64), HEADER_TOC(image_size, iv_imageSize, P9_XIP_UINT32), @@ -2976,7 +2975,9 @@ p9_xip_translate_header(P9XipHeader* o_dest, const P9XipHeader* i_src) #endif o_dest->iv_magic = xipRevLe64(i_src->iv_magic); - o_dest->iv_entryOffset = xipRevLe64(i_src->iv_entryOffset); + o_dest->iv_L1LoaderAddr = xipRevLe64(i_src->iv_L1LoaderAddr); + o_dest->iv_L2LoaderAddr = xipRevLe64(i_src->iv_L2LoaderAddr); + o_dest->iv_kernelAddr = xipRevLe64(i_src->iv_kernelAddr); o_dest->iv_linkAddress = xipRevLe64(i_src->iv_linkAddress); for (i = 0; i < 5; i++) diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h index 1d65b220a..d8cf68ceb 100644 --- a/src/import/chips/p9/xip/p9_xip_image.h +++ b/src/import/chips/p9/xip/p9_xip_image.h @@ -347,18 +347,21 @@ typedef struct /// Contains P9_XIP_MAGIC to identify a P9-XIP image uint64_t iv_magic; - /// The offset of the P9-XIP entry point from the start of the image - uint64_t iv_entryOffset; + /// The entry address of the L1 loader entry point in SEEPROM + uint64_t iv_L1LoaderAddr; + + /// The entry address of the L2 loader entry point in SRAM + uint64_t iv_L2LoaderAddr; + + /// The entry address of Kernel in SRAM + uint64_t iv_kernelAddr; /// The base address used to link the image, as a full relocatable image /// address uint64_t iv_linkAddress; - /// The entry address of base loader - uint64_t iv_entryAddressSBE; - /// Reserved for future expansion - uint64_t iv_reserved64[4]; + uint64_t iv_reserved64[3]; ////////////////////////////////////////////////////////////////////// // Section Table - 4-byte aligned; 16 entries |
