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authorMartin Peschke <mpeschke@de.ibm.com>2015-11-26 18:09:41 +0100
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-02-24 14:59:23 -0600
commit11f529cc8f008ffcb21101b35c002310f1f77ab7 (patch)
treee7cd34548bddc5084cd3b3c44bf4e3b9e6ad9fe3 /src/import/chips/p9/xip
parent5bf35119947758204779c44bf04a18f6e9d8710c (diff)
downloadtalos-hostboot-11f529cc8f008ffcb21101b35c002310f1f77ab7.tar.gz
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P9-XIP image build: initial implementation
This code is supposed to be used for all P9-XIP image build flows, including the ones for the Hardware Image (former Reference Image) and for the SBE IPL Image (located in the ppe repository). It has been derived from SBE-XIP code within the ppe repo (tools/image, sbe/image). This code has been succesfully used to build the SBE IPL image in the ppe repository. This code should is capable of building images, while it does not come with support for putting default values into attributes yet. Changes include: - cut down on number of included header files (eliminating lots of dependencies related to ppe and ekb repos) - a lot of renaming (SBE to P9-XIP) - Makefile cleanup - cleanup of white space damage Todos: - Some files might need to be revisited later, i.e. anything that doesn't come with a p9_xip_ prefix. - We may want to integrate this into ekb build. - The Makefile contains a check for the required compiler version. If the checks fails, manual actions must be taken. For a fully automated build this needs improvement. - The P9-XIP image build code needs to be mirrored to the ppe repo, and the SBE IPL Image build flow should be adapted to used it. - The sbe_default_tool is not included in this port. Change-Id: I0154333770277855c93203859dd4ca9f098b6f01 Original-Change-Id: I6017602fc61787fbb58673bfc2bf046f19526ff4 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23004 Tested-by: Jenkins Server Reviewed-by: Martin Peschke <mpeschke@de.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24740 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/xip')
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diff --git a/src/import/chips/p9/xip/p9_image_help_base.H b/src/import/chips/p9/xip/p9_image_help_base.H
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+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/xip/p9_image_help_base.H $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2015,2016 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+
+#ifndef _P9_IMAGE_HELP_BASE_H_
+#define _P9_IMAGE_HELP_BASE_H_
+
+#include <p9_xip_image.h>
+
+//
+// Various image/ring buffer sizes. Must be used by all users (VBU, FSP, HB, HBI, Cronus)
+//
+const uint32_t MAX_REF_IMAGE_SIZE = 5000000; // Max reference image size.
+const uint32_t FIXED_SEEPROM_WORK_SPACE = 128 * 1024; // Max work space for Seeprom img.
+const uint32_t MAX_SEEPROM_IMAGE_SIZE = 56 * 1024; // Max Seeprom image size.
+const uint32_t FIXED_RING_BUF_SIZE = 60000; // Fixed ring buf size for _fixed.
+
+const uint8_t MAX_VPD_TYPES = 2; // #G and #R, so far.
+#define CHIPLET_ID_MIN 0x00
+#define CHIPLET_ID_MAX 0x1F
+#define CHIPLET_ID_EX_MIN 0x10
+#define CHIPLET_ID_EX_MAX 0x1F
+const uint8_t MAX_CHIPLETS = CHIPLET_ID_MAX - CHIPLET_ID_MIN + 1;
+const uint32_t ASM_RS4_LAUNCH_BUF_SIZE = 24; // Byte size of RS4 launch buffer.
+const uint32_t WF_ENCAP_SIZE = 400; // Byte size of WF encapsulation.
+// (Actually, only 304B but may change.)
+const uint32_t WF_WORST_CASE_SIZE_FAC = 4; // WC WF size = 3x ring length.
+// (Assumes 12B per write.)
+// (4x w/waits instructions.)
+const uint32_t LISTING_STRING_SIZE = 256;
+const uint64_t MAX_UINT64_T = (uint64_t)0xFFFFFFFF << 32 | (uint64_t)0xFFFFFFFF;
+
+const uint8_t RING_SECTION_ID[] =
+{
+ P9_XIP_SECTION_RINGS,
+ P9_XIP_SECTION_OVERLAYS,
+};
+const uint8_t RING_SECTION_ID_SIZE = sizeof(RING_SECTION_ID) / sizeof(RING_SECTION_ID[0]);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Base (shared) ring layout for both RS4 and Wiggle-flip layouts.
+typedef struct
+{
+ uint64_t entryOffset;
+ uint64_t backItemPtr;
+ uint32_t sizeOfThis;
+ uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
+} BaseRingLayout;
+
+// RS4 specific layout.
+typedef struct
+{
+ uint64_t entryOffset;
+ uint64_t backItemPtr;
+ uint32_t sizeOfThis;
+ uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
+ uint32_t ddLevel;
+ uint8_t sysPhase;
+ uint8_t override;
+ uint8_t reserved1;
+ uint8_t reserved2;
+} Rs4RingLayout;
+
+// PairingInfo is used for pairing, or matching, a back pointer address of a
+// ring block with its corresponding TOC name.
+typedef struct
+{
+ uint64_t address; // (in) Holds HOMER backPtr addr of the ring
+ uint8_t vectorpos; // (in) Vector position of fwdPtr [0;31]
+ // max=0 for most VPD rings
+ // max=1 for all non-VPD rings
+ // max=1 for perv_ VPD rings
+ // max=15 for most VPD ex_ rings
+ // max=31 for 16 ex_ chiplets with override
+ char* name; // (out) TOC name
+ uint8_t isvpd; // (out) 0: Non-VPD ring 1: VPD ring
+ uint8_t overridable; // (out) 0: No (most VPD rings) 1: Yes (all non-VPD rings)
+ uint8_t override; // (out) 0: base 1: override
+} PairingInfo;
+
+
+///
+/// ****************************************************************************
+/// Function declares.
+/// ****************************************************************************
+///
+int over_write_ring_data_in_image( void* io_image,
+ const char* i_ringName,
+ const void* i_ringData, // WF or RS4
+ const uint32_t i_sizeRingData, // Byte size
+ const uint8_t i_idxVector,
+ const uint8_t i_override,
+ const uint8_t i_overridable );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_P8_IMAGE_HELP_BASE_H_
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