Adding attribute to turn memory early data on

Performance wants a way to turn memory early data on & off
using just scoms. Adding one attribute to control all the needed
scoms and defaulting everything so that early data is off.

For the L3 disable cp_me by default using scom

Changing the scom cp_me dial to disable cp_me for all systems
after Nimbus DD2.0. This is expected to be the correct setup
for most systems.

We didn't disable the cp_me at the scan, because the scom can
only disable cp_me if ON or allow the scan setting if set OFF. Some
systems might want cp_me enabled by only changing a scom. So the default
is to set cp_me on at the scan and off a the scom. This way only the
scom has to be turned off to enable cp_me.

Also update three scoms in the memory controler that are needed for
early data.

Change-Id: Ib2106ec4b7d26cb084601f2d6eee68833b36d30b
CQ: HW426419
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49261
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49332
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

6 files changed, 86 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
index e42dbd00e..90d79259d 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
@@ -118,6 +118,8 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
         uint64_t l_def_refblock_off_special_case = (((l_def_is_dual_slot == literal_0)
                 && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_4))
                 && (l_def_SLOT0_DRAM_STACK_HEIGHT == literal_2));
+        fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT3_ATTR_ENABLE_MEM_EARLY_DATA_SCOM;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT3, l_TGT3_ATTR_ENABLE_MEM_EARLY_DATA_SCOM));
         fapi2::ATTR_CHIP_EC_FEATURE_HW401780_Type l_TGT4_ATTR_CHIP_EC_FEATURE_HW401780;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW401780, TGT4, l_TGT4_ATTR_CHIP_EC_FEATURE_HW401780));
         fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0;
@@ -329,6 +331,17 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
                 l_scom_buffer.insert<18, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_DISP_OFF );
             }
 
+            if ((l_TGT3_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF))
+            {
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_EN_ALT_ECR_ERR_OFF = 0x0;
+                l_scom_buffer.insert<61, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_EN_ALT_ECR_ERR_OFF );
+            }
+            else if ((l_TGT3_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON))
+            {
+                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_EN_ALT_ECR_ERR_ON = 0x1;
+                l_scom_buffer.insert<61, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_EN_ALT_ECR_ERR_ON );
+            }
+
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010824ull, l_scom_buffer));
         }
         {
@@ -393,8 +406,18 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
                 FAPI_TRY(fapi2::getScom( TGT0, 0x501082bull, l_scom_buffer ));
 
                 l_scom_buffer.insert<45, 1, 63, uint64_t>(literal_0b1 );
-                constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON = 0x1;
-                l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON );
+
+                if ((l_TGT3_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF))
+                {
+                    constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON = 0x1;
+                    l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON );
+                }
+                else if ((l_TGT3_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON))
+                {
+                    constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF = 0x0;
+                    l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF );
+                }
+
                 constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_DISABLE_WRTO_IG_ON = 0x1;
                 l_scom_buffer.insert<44, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_DISABLE_WRTO_IG_ON );
                 constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY_ON = 0x1;
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C
index 2871e6e2c..e4a6e1552 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C
@@ -54,6 +54,8 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec));
         fapi2::ATTR_CHIP_EC_FEATURE_HW398139_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW398139, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139));
+        fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM));
         fapi2::ATTR_RISK_LEVEL_Type l_TGT1_ATTR_RISK_LEVEL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, TGT1, l_TGT1_ATTR_RISK_LEVEL));
         fapi2::ATTR_FREQ_PB_MHZ_Type l_TGT1_ATTR_FREQ_PB_MHZ;
@@ -122,8 +124,16 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
                     && (l_chip_ec == 0x22)) )
             {
-                constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF = 0x0;
-                l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF );
+                if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF))
+                {
+                    constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF = 0x0;
+                    l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF );
+                }
+                else if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON))
+                {
+                    constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_ON = 0x1;
+                    l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_ON );
+                }
             }
 
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index 5b3ba063d..4f5ab5dee 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -233,6 +233,7 @@ HCD_CONST(SGPE_VDM_ENABLE_BIT_POS,                0x04000000)
 HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS,     0x02000000)
 HCD_CONST(SGPE_PHANTOM_HALT_ENABLE_BIT_POS,       0x00800000)
 HCD_CONST(SGPE_IS_SIMULATION_BIT_POS,             0x00400000)
+HCD_CONST(SGPE_ENABLE_MEM_EARLY_DATA_SCOM_POS,    0x00008000)
 HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS,        0x00004000)
 HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS,     0x00002000)
 HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS,       0x00001000)
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 75cd9dcb0..84a72350a 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -879,6 +879,22 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO
 
     FAPI_DBG(" ==================== SGPE Header Flags =================");
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM,
+                           FAPI_SYSTEM,
+                           attrVal),
+             "Error from FAPI_ATTR_GET for attribute ATTR_ENABLE_MEM_EARLY_DATA_SCOM");
+
+    //Attribute set to 0x01 for CHIP_IS_NODE
+    if( attrVal == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON )
+    {
+        sgpeFlag |= SGPE_ENABLE_MEM_EARLY_DATA_SCOM_POS;
+    }
+
+    FAPI_DBG("Memory Early Data Scom Enabled:   %s", (
+    attrVal == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON) ? "TRUE" : "FALSE" );
+
+    ///
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE,
                            FAPI_SYSTEM,
                            attrVal),
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index ec28e402a..124ff2b72 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2400,6 +2400,23 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_PRE_CACHE_DD21_SETTINGS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Not workaround or defect related. Just new dials to be set that are new in the caches for DD2.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_DISABLE_CP_ME</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 9929b61ce..86dff9770 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -1347,6 +1347,21 @@
   <persistRuntime/>
   <initToZero/>
 </attribute>
+<!-- ******************************************************************** -->
+<attribute>
+  <id>ATTR_ENABLE_MEM_EARLY_DATA_SCOM</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Enable early data from Memory. This also enable cp_me from L3.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <platInit/>
+  <initToZero/>
+</attribute>
 <!-- ********************************************************************** -->
 
 </attributes>