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author | Chris Hanudel <chanudel@us.ibm.com> | 2017-04-14 10:55:06 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-22 17:12:48 -0400 |
commit | ee309b91f8f54e0171154fa79b579d735453edac (patch) | |
tree | 381d370b948e5bdc931e0e72418368fdf75d8cc1 /src/import/chips/p9/procedures | |
parent | 84076c30975d55451ce94680ce623d92d6326593 (diff) | |
download | talos-hostboot-ee309b91f8f54e0171154fa79b579d735453edac.tar.gz talos-hostboot-ee309b91f8f54e0171154fa79b579d735453edac.zip |
Disable P9 NX RNG Read Delay Randomizer
Change-Id: I94fb1bfe4321b8085b66ec349eca5b0100b8573f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39289
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39290
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C index 40fb65a99..775cf9523 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C @@ -119,6 +119,10 @@ const uint16_t NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD2 = 0x7333; // sample rate match threshold maximum (64k * 0.55 = 36,044) const uint16_t NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD2 = 0x8CCC; +// RNG Read Delay Parameters Register +// Read Retry Ratio (0 = 31/32, 1 = 15/16, 2 = 29/32 ... 15 = 1/2 ... 31 = disabled) +const uint8_t NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD1 = 0x1F; +const uint8_t NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD2 = 0x1F; // RNG Status And Control Register constants (Applies to both) const bool NX_RNG_CFG_CONDITIONER_MASK_TOGGLE = false; @@ -152,6 +156,7 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) fapi2::buffer<uint64_t> l_rng_st1_data; fapi2::buffer<uint64_t> l_rng_st2_data; fapi2::buffer<uint64_t> l_rng_st3_data; + fapi2::buffer<uint64_t> l_rng_rdelay_data; uint8_t l_dd1 = 0; uint8_t l_HW403701 = 0; @@ -184,6 +189,8 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) "Error from getScom (NX RNG Self Test Register 1)"); FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_ST3, l_rng_st3_data), "Error from getScom (NX RNG Self Test Register 3)"); + FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_RDELAY, l_rng_rdelay_data), + "Error from putScom (NX RNG Read Delay Parameters Register)"); if (l_dd1 != 0) { @@ -222,6 +229,10 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) (NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD1); l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX, PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN> (NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD1); + + // configure RNG Read Delay Parameters Register + l_rng_rdelay_data.insertFromRight<PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO, PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN> + (NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD1); } else { @@ -260,6 +271,10 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) (NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD2); l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX, PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN> (NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD2); + + // configure RNG Read Delay Parameters Register + l_rng_rdelay_data.insertFromRight<PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO, PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN> + (NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD2); } FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_ST0, l_rng_st0_data), @@ -271,6 +286,9 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_ST3, l_rng_st3_data), "Error from putScom (NX RNG Self Test Register 3)"); + FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_RDELAY, l_rng_rdelay_data), + "Error from putScom (NX RNG Read Delay Parameters Register)"); + // 4. If RNG is not broken then host boot sets rng_enable =1. // update RNG Status and Control Register to engage initialization test FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data), @@ -308,4 +326,3 @@ fapi_try_exit: FAPI_INF("End"); return fapi2::current_err; } - |