PLL configuration updates -- permit e2e bypass execution

p9_sbe_attr_setup
p9_setup_sbe_config
  transmit PLL bypass controls through MBOX Scratch 4 bits 16:20
  transmit PLL mux controls through MBOX Scratch 5 bits 12:31

p9_common_poweronoff
  increase polling delays to account for refclock speed

p9_hcd_cache_dpll_setup
  permit DPLL execution in bypass, based on ATTR_DPLL_BYPASS

p9_sbe_npll_setup
  permit NEST PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_mem_pll_setup
  permit MEM PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_chiplet_pll_setup
  permit X/O/PCI PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_tp_switch_gears
  skip adjustment of i2c bit divisor, based on ATTR_NEST_MEM_X_O_PCI_BYPASS

p9_sbe_attributes.xml
hb_temp_defaults.xml
  add defaults to enable platform CI

Change-Id: Icba6aee79d90b0280ba4818afd92c344c52f52ef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28611
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28614
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 169 insertions, 66 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_setup.C
index c26e5fe54..9c991d15d 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_setup.C
@@ -50,18 +50,23 @@ enum P9_MEM_PLL_SETUP_Private_Constants
 };
 
 
-fapi2::ReturnCode p9_mem_pll_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet)
+fapi2::ReturnCode p9_mem_pll_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     uint8_t l_read_attr = 0;
     fapi2::buffer<uint64_t> l_data64;
+    uint8_t l_mem_bypass;
 
     FAPI_INF("Entering ...");
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chiplet, l_read_attr));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_mem_bypass),
+             "Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS");
 
-    if ( !l_read_attr )
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr),
+             "Error from FAPI_ATTR_GET (ATTR_MC_SYNC_MODE)");
+
+    if (!l_read_attr )
     {
-        for (auto l_chplt_trgt :  i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV>
+        for (auto l_chplt_trgt :  i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
              (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
         {
             FAPI_DBG("Drop PLDY bypass of Progdelay logic");
@@ -76,42 +81,45 @@ fapi2::ReturnCode p9_mem_pll_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
             l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>();
             FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL1_WAND, l_data64));
 
-            FAPI_DBG("Drop PLL test enable");
-            l_data64.flush<1>();
-            //NET_CTRL0.TP_PLL_TEST_EN_DC
-            l_data64.clearBit<PERV_1_NET_CTRL0_PLL_TEST_EN>();
-            FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL0_WAND, l_data64));
-
-            FAPI_DBG("Drop PLL reset");
-            l_data64.flush<1>();
-            //NET_CTRL0.TP_PLLRST_DC
-            l_data64.clearBit<PERV_1_NET_CTRL0_PLL_RESET>();
-            FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL0_WAND, l_data64));
-
-            fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
-
-            FAPI_DBG("check PLL lock");
-
-            //Getting PLL_LOCK_REG register value
-            FAPI_TRY(fapi2::getScom(l_chplt_trgt, PERV_PLL_LOCK_REG,
-                                    l_data64)); //l_read_reg = PERV.PLL_LOCK_REG
-            FAPI_ASSERT(l_data64.getBit<0>() == 1,
-                        fapi2::MEM_PLL_LOCK_ERR()
-                        .set_MEM_PLL_READ(l_data64),
-                        "ERROR:MEM PLL LOCK NOT SET");
-
-            FAPI_DBG("Drop PLL Bypass");
-            l_data64.flush<1>();
-            //NET_CTRL0.TP_PLLBYP_DC =  0
-            l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>();
-            FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL0_WAND, l_data64));
-
-            //OPCG_ALIGN.scan_ratio=0b00011
-            FAPI_DBG("Set scan ratio to 4:1");
-            FAPI_TRY(fapi2::getScom(l_chplt_trgt, PERV_OPCG_ALIGN, l_data64));
-            l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
-            (OPCG_ALIGN_SCAN_RATIO);
-            FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_OPCG_ALIGN, l_data64));
+            if (l_mem_bypass == 0)
+            {
+                FAPI_DBG("Drop PLL test enable");
+                l_data64.flush<1>();
+                //NET_CTRL0.TP_PLL_TEST_EN_DC
+                l_data64.clearBit<PERV_1_NET_CTRL0_PLL_TEST_EN>();
+                FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL0_WAND, l_data64));
+
+                FAPI_DBG("Drop PLL reset");
+                l_data64.flush<1>();
+                //NET_CTRL0.TP_PLLRST_DC
+                l_data64.clearBit<PERV_1_NET_CTRL0_PLL_RESET>();
+                FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL0_WAND, l_data64));
+
+                fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+                FAPI_DBG("check PLL lock");
+
+                //Getting PLL_LOCK_REG register value
+                FAPI_TRY(fapi2::getScom(l_chplt_trgt, PERV_PLL_LOCK_REG,
+                                        l_data64)); //l_read_reg = PERV.PLL_LOCK_REG
+                FAPI_ASSERT(l_data64.getBit<0>() == 1,
+                            fapi2::MEM_PLL_LOCK_ERR()
+                            .set_MEM_PLL_READ(l_data64),
+                            "ERROR:MEM PLL LOCK NOT SET");
+
+                FAPI_DBG("Drop PLL Bypass");
+                l_data64.flush<1>();
+                //NET_CTRL0.TP_PLLBYP_DC =  0
+                l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>();
+                FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_NET_CTRL0_WAND, l_data64));
+
+                //OPCG_ALIGN.scan_ratio=0b00011
+                FAPI_DBG("Set scan ratio to 4:1");
+                FAPI_TRY(fapi2::getScom(l_chplt_trgt, PERV_OPCG_ALIGN, l_data64));
+                l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
+                (OPCG_ALIGN_SCAN_RATIO);
+                FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_OPCG_ALIGN, l_data64));
+            }
 
             //Reset PCB Slave error register
             FAPI_DBG("Reset PCB Slave error register");
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index 3a9aff936..6a5dd5ead 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -57,9 +57,20 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3,
     ATTR_BOOT_FREQ_MULT_STARTBIT = 0,
     ATTR_BOOT_FREQ_MULT_LENGTH = 16,
+    ATTR_CP_FILTER_BYPASS_BIT = 16,
+    ATTR_SS_FILTER_BYPASS_BIT = 17,
+    ATTR_IO_FILTER_BYPASS_BIT = 18,
+    ATTR_DPLL_BYPASS_BIT = 19,
+    ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT = 20,
     ATTR_NEST_PLL_BUCKET_STARTBIT = 24,
-    ATTR_NEST_PLL_BUCKET_LENGTH = 8
-
+    ATTR_NEST_PLL_BUCKET_LENGTH = 8,
+    ATTR_CC_IPL_BIT = 0,
+    ATTR_INIT_ALL_CORES_BIT = 1,
+    ATTR_RISK_LEVEL_BIT = 2,
+    ATTR_DISABLE_HBBL_VECTORS_BIT = 3,
+    ATTR_MC_SYNC_MODE_BIT = 4,
+    ATTR_PLL_MUX_STARTBIT = 12,
+    ATTR_PLL_MUX_LENGTH = 20
 };
 
 
@@ -70,7 +81,6 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     fapi2::buffer<uint32_t> l_read_scratch8 = 0;
     fapi2::buffer<uint8_t> l_read_1 = 0;
     fapi2::buffer<uint8_t> l_read_2 = 0;
-    fapi2::buffer<uint8_t> l_read_3 = 0;
     fapi2::buffer<uint16_t> l_read_4 = 0;
     fapi2::buffer<uint32_t> l_read_5 = 0;
     fapi2::buffer<uint32_t> l_read_6 = 0;
@@ -150,11 +160,29 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     }
     //set_scratch4_reg
     {
+        uint8_t l_cp_filter_bypass;
+        uint8_t l_ss_filter_bypass;
+        uint8_t l_io_filter_bypass;
+        uint8_t l_dpll_bypass;
+        uint8_t l_nest_mem_x_o_pci_bypass;
+
         FAPI_DBG("Reading Scratch_reg4");
         //Getting SCRATCH_REGISTER_4 register value
         FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
                                         l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_4
 
+        FAPI_DBG("Reading PLL bypass attributes");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass),
+                 "Error from FAPI_ATTR_GET (ATTR_CP_FILTER_BYPASS");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, l_ss_filter_bypass),
+                 "Error from FAPI_ATTR_GET (ATTR_SS_FILTER_BYPASS");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass),
+                 "Error from FAPI_ATTR_GET (ATTR_IO_FILTER_BYPASS");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass),
+                 "Error from FAPI_ATTR_GET (ATTR_DPLL_BYPASS");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass),
+                 "Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS");
+
         FAPI_DBG("Reading ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
@@ -162,6 +190,12 @@ fapi2::ReturnCode p9_setup_sbe_config(const
         l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
         l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);
 
+        l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1);
+        l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1);
+        l_read_scratch_reg.writeBit<ATTR_IO_FILTER_BYPASS_BIT>(l_io_filter_bypass & 0x1);
+        l_read_scratch_reg.writeBit<ATTR_DPLL_BYPASS_BIT>(l_dpll_bypass & 0x1);
+        l_read_scratch_reg.writeBit<ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT>(l_nest_mem_x_o_pci_bypass & 0x1);
+
         FAPI_DBG("Setting up value of Scratch_reg4");
         //Setting SCRATCH_REGISTER_4 register value
         //CFAM.SCRATCH_REGISTER_4 = l_read_scratch_reg
@@ -172,60 +206,80 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     }
     //set_scratch5_reg
     {
+        uint8_t l_system_ipl_phase;
+        uint8_t l_force_all_cores;
+        uint8_t l_risk_level;
+        uint8_t l_disable_hbbl_vectors;
+        uint32_t l_pll_mux;
+        uint8_t l_mc_sync_mode;
+
         FAPI_DBG("Reading Scratch_reg5");
         //Getting SCRATCH_REGISTER_5 register value
         FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
                                         l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_5
 
-        FAPI_DBG("Reading the control flags : SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_2));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM,
-                               l_read_3));
+        FAPI_DBG("Reading control flag attributes");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
 
         // set cache contained flag
-        if (l_read_1 == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
+        if (l_system_ipl_phase == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
         {
-            l_read_scratch_reg.setBit<0>();
+            l_read_scratch_reg.setBit<ATTR_CC_IPL_BIT>();
         }
         else
         {
-            l_read_scratch_reg.clearBit<0>();
+            l_read_scratch_reg.clearBit<ATTR_CC_IPL_BIT>();
         }
 
         // set all cores flag
-        if (l_read_3)
+        if (l_force_all_cores)
         {
-            l_read_scratch_reg.setBit<1>();
+            l_read_scratch_reg.setBit<ATTR_INIT_ALL_CORES_BIT>();
         }
         else
         {
-            l_read_scratch_reg.clearBit<1>();
+            l_read_scratch_reg.clearBit<ATTR_INIT_ALL_CORES_BIT>();
         }
 
         // set risk level flag
-        if (l_read_2 == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
+        if (l_risk_level == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
         {
-            l_read_scratch_reg.setBit<2>();
+            l_read_scratch_reg.setBit<ATTR_RISK_LEVEL_BIT>();
         }
         else
         {
-            l_read_scratch_reg.clearBit<2>();
+            l_read_scratch_reg.clearBit<ATTR_RISK_LEVEL_BIT>();
         }
 
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM,
-                               l_read_1));
-
         // set disable of HBBL exception vector flag
-        if (l_read_1 == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)
+        if (l_disable_hbbl_vectors == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)
         {
-            l_read_scratch_reg.setBit<3>();
+            l_read_scratch_reg.setBit<ATTR_DISABLE_HBBL_VECTORS_BIT>();
         }
         else
         {
-            l_read_scratch_reg.clearBit<3>();
+            l_read_scratch_reg.clearBit<ATTR_DISABLE_HBBL_VECTORS_BIT>();
         }
 
+        // set MC sync mode
+        if (l_mc_sync_mode)
+        {
+            l_read_scratch_reg.setBit<ATTR_MC_SYNC_MODE_BIT>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<ATTR_MC_SYNC_MODE_BIT>();
+        }
+
+        FAPI_DBG("Reading PLL mux attributes");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
+        // set PLL MUX bits
+        l_read_scratch_reg.insert<ATTR_PLL_MUX_STARTBIT, ATTR_PLL_MUX_LENGTH, 0>(l_pll_mux);
+
         FAPI_DBG("Setting up value of Scratch_reg5");
         //Setting SCRATCH_REGISTER_5 register value
         //CFAM.SCRATCH_REGISTER_5 = l_read_scratch_reg
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index 0e6bc542f..045b93e43 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -34,6 +34,10 @@
   <description>setup clock mux settings</description>
   <valueType>uint32</valueType>
   <platInit/>
+  <!-- TODO: Story 155081
+       Not supposed to be writeable, PPE needs to resolve this issue in
+       p9_sbe_attr_setup.C -->
+  <writeable/>
 </attribute>
 
 <attribute>
@@ -629,28 +633,65 @@
 <attribute>
     <id>ATTR_CP_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>To skip the locking sequence and check for lock of CP PLL</description>
+    <description>To skip the locking sequence and check for lock of CP filter PLL</description>
     <valueType>uint8</valueType>
     <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
 </attribute>
 
 <attribute>
     <id>ATTR_SS_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>To skip the locking sequence and check for lock of SS PLL</description>
+    <description>To skip the locking sequence and check for lock of SS filter PLL</description>
     <valueType>uint8</valueType>
     <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
 </attribute>
 
 <attribute>
     <id>ATTR_IO_FILTER_BYPASS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>To skip the locking sequence and check for lock of IO PLL</description>
+    <description>To skip the locking sequence and check for lock of IO filter PLL</description>
     <valueType>uint8</valueType>
     <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
 </attribute>
 
 <attribute>
+    <id>ATTR_DPLL_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Skip locking sequence and check for lock of DPLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_NEST_MEM_X_O_PCI_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <!-- TODO: Story 155081
+         Not supposed to be writeable, PPE needs to resolve this issue in
+         p9_sbe_attr_setup.C -->
+    <writeable/>
+</attribute>
+
+
+<attribute>
   <id>ATTR_TARGET_HAS_POWER</id>
   <targetType>TARGET_TYPE_PERV</targetType>
   <description>Functional Target has power</description>