FIR updates

  p9.cme.scan.initfile
    add CME LFIR settings
    add EQ pervasive LFIR/XFIR settings

  p9.npu.scom.initfile
    update NPU_0/NPU_1 LFIR settings

  p9.psi.scom.initfile
    add PSI LFIR settings

  p9_sbe_scominit
    add LPC LFIR settings
    update placeholder for pervasive LFIR/XFIR settings
    (for Nest/XBUS/MC/OBUS/PCIE)

  p9_sbe_tp_chiplet_init3
    update TP pervasive LFIR settings

  p9_pcie_config
    fix bug affecting PHBBAR programming (causing invalid BAR matches)

  p9_pcie_scominit
    update PEC LFIR settings

  p9_setup_bars_defs
    update MCD LFIR settings

Change-Id: I8aaf7f40e96cde2fbd6e44fd0451e0add6584b77
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29197
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29232
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

5 files changed, 104 insertions, 13 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
index a193ddfe5..5da7c0653 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
@@ -34,8 +34,12 @@ constexpr auto literal_3 = 3;
 constexpr auto literal_1 = 1;
 constexpr auto literal_0 = 0;
 constexpr auto literal_0x0 = 0x0;
-constexpr auto literal_0x1111111111111111 = 0x1111111111111111;
-constexpr auto literal_0x0000000000000000 = 0x0000000000000000;
+constexpr auto literal_0x009A48180F01FFFF = 0x009A48180F01FFFF;
+constexpr auto literal_0x7F60B04500AE0000 = 0x7F60B04500AE0000;
+constexpr auto literal_0xFF65B04700FE0000 = 0xFF65B04700FE0000;
+constexpr auto literal_0x5550F40000000003 = 0x5550F40000000003;
+constexpr auto literal_0xAAA70A5DF0000000 = 0xAAA70A5DF0000000;
+constexpr auto literal_0xAAAF0BFFF0000000 = 0xAAAF0BFFF0000000;
 
 fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0,
                               const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
@@ -201,7 +205,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
 
             {
-                l_scom_buffer.insert<uint64_t> (literal_0x1111111111111111, 0, 64, 0 );
+                l_scom_buffer.insert<uint64_t> (literal_0x009A48180F01FFFF, 0, 64, 0 );
             }
 
             l_rc = fapi2::putScom(TGT0, 0x5011403ull, l_scom_buffer);
@@ -223,7 +227,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
 
             {
-                l_scom_buffer.insert<uint64_t> (literal_0x0000000000000000, 0, 64, 0 );
+                l_scom_buffer.insert<uint64_t> (literal_0x7F60B04500AE0000, 0, 64, 0 );
             }
 
             l_rc = fapi2::putScom(TGT0, 0x5011406ull, l_scom_buffer);
@@ -245,7 +249,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
 
             {
-                l_scom_buffer.insert<uint64_t> (literal_0x0000000000000000, 0, 64, 0 );
+                l_scom_buffer.insert<uint64_t> (literal_0xFF65B04700FE0000, 0, 64, 0 );
             }
 
             l_rc = fapi2::putScom(TGT0, 0x5011407ull, l_scom_buffer);
@@ -258,6 +262,28 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         }
 
         {
+            l_rc = fapi2::getScom( TGT0, 0x5011443ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x5011443ull)");
+                break;
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x5550F40000000003, 0, 64, 0 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x5011443ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x5011443ull)");
+                break;
+            }
+        }
+
+        {
             l_rc = fapi2::getScom( TGT0, 0x5011446ull, l_scom_buffer );
 
             if (l_rc)
@@ -267,7 +293,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
 
             {
-                l_scom_buffer.insert<uint64_t> (literal_0x0000000000000000, 0, 64, 0 );
+                l_scom_buffer.insert<uint64_t> (literal_0xAAA70A5DF0000000, 0, 64, 0 );
             }
 
             l_rc = fapi2::putScom(TGT0, 0x5011446ull, l_scom_buffer);
@@ -289,7 +315,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
 
             {
-                l_scom_buffer.insert<uint64_t> (literal_0x0000000000000000, 0, 64, 0 );
+                l_scom_buffer.insert<uint64_t> (literal_0xAAAF0BFFF0000000, 0, 64, 0 );
             }
 
             l_rc = fapi2::putScom(TGT0, 0x5011447ull, l_scom_buffer);
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C
index f4b8547d7..fb04ebbae 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C
@@ -29,6 +29,8 @@
 
 using namespace fapi2;
 
+constexpr auto literal_0xFE00000000000000 = 0xFE00000000000000;
+constexpr auto literal_0x0000000000000000 = 0x0000000000000000;
 constexpr auto literal_0b00111001000000101111111111111 = 0b00111001000000101111111111111;
 constexpr auto literal_0b00000000000000000000000000000 = 0b00000000000000000000000000000;
 constexpr auto literal_0b11000110001010010000000000000 = 0b11000110001010010000000000000;
@@ -43,6 +45,69 @@ fapi2::ReturnCode p9_psi_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
     {
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
+            l_rc = fapi2::getScom( TGT0, 0x4011803ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x4011803ull)");
+                break;
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0xFE00000000000000, 0, 7, 0 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x4011803ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x4011803ull)");
+                break;
+            }
+        }
+        {
+            l_rc = fapi2::getScom( TGT0, 0x4011806ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x4011806ull)");
+                break;
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x0000000000000000, 0, 7, 0 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x4011806ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x4011806ull)");
+                break;
+            }
+        }
+        {
+            l_rc = fapi2::getScom( TGT0, 0x4011807ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x4011807ull)");
+                break;
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x0000000000000000, 0, 7, 0 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x4011807ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x4011807ull)");
+                break;
+            }
+        }
+        {
             l_rc = fapi2::getScom( TGT0, 0x5012903ull, l_scom_buffer );
 
             if (l_rc)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
index eb141d60b..f3f269f62 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
@@ -309,8 +309,8 @@ fapi2::ReturnCode p9_pcie_config(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHI
         l_register_bar += l_register_bar_offsets[l_phb_id];
         FAPI_DBG("phb%i bar1 addr: %#lx", l_phb_id, l_register_bar());
         l_register_bar = l_register_bar << P9_PCIE_CONFIG_BAR_SHIFT;
-        FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_MMIOBAR1_REG, l_register_bar),
-                 "Error from putScom (PHB_MMIOBAR1_REG)");
+        FAPI_TRY(fapi2::putScom(l_phb_chiplets, PHB_PHBBAR_REG, l_register_bar),
+                 "Error from putScom (PHB_PHBBAR_REG)");
 
         // step 23: NestBase+StackBase+0x14<software programmed>Set Base
         // addressress Enable Register (BARE)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
index d85d0d0bd..2a7746a84 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
@@ -173,12 +173,12 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
         FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_FIR_ACTION0_REG, l_buf));
 
         // Phase1 init step 6 (Set FIR action1)
-        l_buf = 0xFFFFFFFFF8000000;
+        l_buf = 0xE79E79E000000000ULL;
         FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
         FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_FIR_ACTION1_REG, l_buf));
 
         // Phase1 init step 7 (Set FIR mask)
-        l_buf = 0xFFFFFFFFF8000000;
+        l_buf = 0x1861861FF8000000ULL;
         FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
         FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_FIR_MASK_REG, l_buf));
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
index f0a97d393..0c4e56057 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H
@@ -304,8 +304,8 @@ struct p9_setup_bars_addr_range
 //
 
 const uint64_t MCD_FIR_ACTION0 = 0x0000000000000000ULL;
-const uint64_t MCD_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
-const uint64_t MCD_FIR_MASK    = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t MCD_FIR_ACTION1 = 0x8030000000000000ULL;
+const uint64_t MCD_FIR_MASK    = 0x4C40000000000000ULL;
 
 
 //