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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2018-02-21 09:31:25 +0100 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-02-12 16:49:00 -0600 |
| commit | 959908a2a341c4dfd607c7ad142cd49ecd62d541 (patch) | |
| tree | 54f6773b7fdc80db211b97b5c284a16b46cec38b /src/import/chips/p9/procedures | |
| parent | 4f5f6328360aa9621b6f89ad40aca4cd3a82d5f3 (diff) | |
| download | talos-hostboot-959908a2a341c4dfd607c7ad142cd49ecd62d541.tar.gz talos-hostboot-959908a2a341c4dfd607c7ad142cd49ecd62d541.zip | |
p9_sbe_lpc_init: Add final check for errors
Add an external FFDC collection procedure that will dump the LPC
register spaces, make sure it is called if after LPC setup an OPB
error is registered.
Change-Id: Ia4b31ced6c322cb56a7d408f66ac07c459bf5d9a
Original-Change-Id: I91046a6a3814ba94abd878f860e08f1b1338390b
CQ: SW435433
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57803
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71482
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C | 11 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H | 2 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C index 930fe7571..829db55e9 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C @@ -176,6 +176,17 @@ fapi2::ReturnCode p9_sbe_lpc_init( FAPI_TRY(lpc_write(i_target_chip, LPCM_LPC_MASTER_TIMEOUT_REG, LPCM_LPC_MASTER_TIMEOUT_VALUE), "Error trying to set up the LPC host controller timeout"); + //------------------------------------------------------------------------------------------ + //--- STEP 4: Check that everyone is happy + //------------------------------------------------------------------------------------------ + FAPI_TRY(lpc_read(i_target_chip, LPCM_OPB_MASTER_STATUS_REG, l_data32), + "Error reading OPB master status register"); + FAPI_ASSERT(0 == (l_data32 & LPCM_OPB_MASTER_STATUS_ERROR_BITS), + fapi2::LPC_OPB_ERROR(). + set_FFDC_TARGET_CHIP(i_target_chip). + set_TARGET_CHIP(i_target_chip), + "The OPB master indicated an error after LPC setup"); + FAPI_DBG("p9_sbe_lpc_init: Exiting ..."); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H index 0c1fe9998..e68acd499 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H @@ -54,6 +54,8 @@ extern "C" const uint64_t LPC_LRESET_OE = 23; const uint64_t LPC_LRESET_OUT = 22; const uint32_t LPC_LRESET_DELAY_NS = 200000; + const uint32_t LPCM_OPB_MASTER_STATUS_REG = 0xC0010000; + const uint32_t LPCM_OPB_MASTER_STATUS_ERROR_BITS = 0x20000FC3; const uint32_t LPCM_OPB_MASTER_CONTROL_REG = 0xC0010008; const uint32_t LPCM_OPB_MASTER_CONTROL_REG_TIMEOUT_ENABLE = 2; const uint32_t LPCM_OPB_MASTER_TIMEOUT_REG = 0xC0010040; |
