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| author | Andre Marin <aamarin@us.ibm.com> | 2017-06-09 18:04:10 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-14 09:42:41 -0400 |
| commit | 7074cfc250e019e570573891e903cc44130dee24 (patch) | |
| tree | 00f21c439c2021034418be3ed44373ce19eeb908 /src/import/chips/p9/procedures | |
| parent | 0116e1f975aa63d61a4d5d1457cc35247829b8db (diff) | |
| download | talos-hostboot-7074cfc250e019e570573891e903cc44130dee24.tar.gz talos-hostboot-7074cfc250e019e570573891e903cc44130dee24.zip | |
Double POR timings (tMOD, tMRD, and tZQ) for more margin per lab
Change-Id: Ia1e575d93370372ae6bcb393258bb6f95e324874
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41639
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41641
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C | 18 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C | 8 |
2 files changed, 17 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index 515f45296..3805a7d5c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -84,17 +84,21 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, { FAPI_INF("ddr4::mrs_load %s", mss::c_str(i_target)); + // Doubling tMRD delay to increase margin per lab request + const size_t DOUBLE_TMRD = 2 * mss::tmrd(); + const size_t DOUBLE_TMOD = 2 * mss::tmod(i_target); + static const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = { // JEDEC ordering of MRS per DDR4 power on sequence - { 3, mrs03, mrs03_decode, mss::tmrd() }, - { 6, mrs06, mrs06_decode, mss::tmrd() }, - { 5, mrs05, mrs05_decode, mss::tmrd() }, - { 4, mrs04, mrs04_decode, mss::tmrd() }, - { 2, mrs02, mrs02_decode, mss::tmrd() }, - { 1, mrs01, mrs01_decode, mss::tmrd() }, + { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, + { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, + { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, + { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, + { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, + { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, // We need to wait tmod before zqcl, a non-mrs command - { 0, mrs00, mrs00_decode, mss::tmod(i_target) }, + { 0, mrs00, mrs00_decode, DOUBLE_TMOD }, }; std::vector< uint64_t > l_ranks; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C index b92c9086d..e69e06130 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C @@ -69,8 +69,12 @@ fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM> // Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_target, i_rank); - l_inst.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, - MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(tDLLK + mss::tzqinit()); + // Doubling tZQ to better margin per lab request + { + const size_t DELAY = 2 * (tDLLK + mss::tzqinit()); + l_inst.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, + MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(DELAY); + } // There's nothing to decode here. FAPI_INF("ZQCL 0x%016llx:0x%016llx %s:rank %d", |
