Fix occ_control and pba_init HWP for OCC bringup

Change-Id: I048849d389e0731ed499a2860180400300f883ec
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27711
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27712
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

2 files changed, 42 insertions, 16 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C
index ed97b601c..737b113cc 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C
@@ -58,6 +58,7 @@ enum
     CTR               = 9,
     OCC_BOOT_OFFSET   = 0x40,
     OCC_SRAM_BOOT_ADDR = 0xFFF40000,
+    OCC_SRAM_BOOT_ADDR2 = 0xFFF40002,
     OCC_MEM_BOOT_PGMADDR = 0xFFF40000,
 };
 
@@ -148,6 +149,7 @@ uint32_t ppc_mtspr( const uint16_t i_Rs, const uint16_t i_Spr )
 {
     uint32_t mtsprInstOpcode = 0;
     mtsprInstOpcode = OPCODE_31 << (31 - 5);
+    mtsprInstOpcode |= i_Rs << (31 - 10);
     uint32_t temp = (( i_Spr & 0x03FF ) << (31 - 20));
     mtsprInstOpcode |= ( temp  & 0x0000F800 ) << 5;  // Perform swizzle
     mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5;  // Perform swizzle
@@ -160,14 +162,16 @@ uint32_t ppc_mtspr( const uint16_t i_Rs, const uint16_t i_Spr )
 /**
  * @brief Creates and loads the OCC memory boot launcher
  * @param[in] i_target  Chip target
- * @return returns 32 bit instruction representing mtspr instruction.
+ * @param[in] i_data64  32 bit instruction representing the branch
+ *                      instruction to the SRAM boot loader
+ * @return returns RC
  */
 fapi2::ReturnCode bootMemory(
-    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    fapi2::buffer<uint64_t>& i_data64)
 {
     static const uint32_t SRAM_PROGRAM_SIZE = 2;  // in double words
     uint64_t l_sram_program[SRAM_PROGRAM_SIZE];
-    fapi2::buffer<uint64_t> l_data64;
     fapi2::ReturnCode l_rc;
     uint32_t l_ocb_length_act = 0;
 
@@ -190,10 +194,10 @@ fapi2::ReturnCode bootMemory(
     FAPI_DBG("ppc_ori: 0x%08X with data 0x%08X",
              ppc_ori(1, 1, OCC_BOOT_OFFSET), OCC_BOOT_OFFSET);
 
-    // mtctr (mtspr CTR, r1 )
-    l_sram_program[1] = ((uint64_t)ppc_mtspr(CTR, 1) << 32);
+    // mtctr (mtspr r1, CTR )
+    l_sram_program[1] = ((uint64_t)ppc_mtspr(1, CTR) << 32);
     FAPI_DBG("ppc_mtspr: 0x%08X with spr 0x%08X",
-             ppc_mtspr(CTR, 1), CTR);
+             ppc_mtspr(1, CTR), CTR);
 
     // bctr
     l_sram_program[1] |= ppc_bctr();
@@ -218,12 +222,8 @@ fapi2::ReturnCode bootMemory(
                 .set_LENGTH(SRAM_PROGRAM_SIZE),
                 "OCC memory boot launcher length mismatch");
 
-    // b OCC_SRAM_BOOT_ADDR
-    l_data64.insertFromRight<0, 32>(ppc_b(OCC_SRAM_BOOT_ADDR));
-
-    // Write to SBV3
-    FAPI_TRY(fapi2::putScom(i_target, PU_SRAM_SRBV3_SCOM, l_data64),
-             "SRAM Boot Vector 3");
+    // b OCC_SRAM_BOOT_ADDR2
+    i_data64.insertFromRight<0, 32>(ppc_b(OCC_SRAM_BOOT_ADDR2));
 
 fapi_try_exit:
     // Channel 1 returned to Linear Stream, Circular upon exit
@@ -308,7 +308,7 @@ fapi2::ReturnCode p9_pm_occ_control
         else if (i_ppc405_boot_ctrl == p9occ_ctrl::PPC405_BOOT_MEM)
         {
             FAPI_INF("Setting up for memory boot");
-            FAPI_TRY(bootMemory(i_target), , "Booting from Memory Failed");
+            FAPI_TRY(bootMemory(i_target, l_data64), "Booting from Memory Failed");
         }
         else
         {
@@ -438,6 +438,11 @@ fapi2::ReturnCode p9_pm_occ_control
             FAPI_TRY(fapi2::putScom(i_target,
                                     PU_OCB_PIB_OCR_CLEAR,
                                     BIT(OCB_PIB_OCR_OCR_DBG_HALT_BIT)));
+            // Set the reset bit
+            FAPI_TRY(fapi2::putScom(i_target,
+                                    PU_OCB_PIB_OCR_OR,
+                                    BIT(OCB_PIB_OCR_CORE_RESET_BIT)));
+
             // Clear the reset bit
             FAPI_TRY(fapi2::putScom(i_target,
                                     PU_OCB_PIB_OCR_CLEAR,
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C
index 57fbf3e6f..6bf8ad4da 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C
@@ -529,7 +529,7 @@ fapi_try_exit:
 ///
 /// PBA slave 0 is used to boot the SGPE and the OCC PPC405.
 ///
-/// PBA slave 1 is not used and not setup.
+/// PBA slave 1 is used to boot the OCC PPC405.
 
 /// PBA slave 2 is used to boot the PGPE.  It is setup as a read/write slave
 /// as the PGPE as to write to HOMER memory during this phase.
@@ -618,8 +618,29 @@ pba_slave_setup_boot_phase(
     FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL0_SCOM, l_data64),
              "Failed to set Slave 0 control register");
 
-    FAPI_INF("Skipping PBA Slave 1 ...");
-    // Slave 1 is not used during Boot phase
+    FAPI_INF("Initialize PBA Slave 1 ...");
+    // Slave 1 (405 ICU/DCU).  This is a read/write slave.  Write gethering is
+    // allowed, but with the shortest possible timeout. This slave is
+    // effectively disabled soon after IPL.
+
+    ps.value = 0;
+    ps.fields.enable = 1;
+    ps.fields.mid_match_value = OCI_MASTER_ID_ICU & OCI_MASTER_ID_DCU;
+    ps.fields.mid_care_mask   = OCI_MASTER_ID_ICU & OCI_MASTER_ID_DCU;
+
+    ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
+    ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
+    ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
+    ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
+    ps.fields.buf_alloc_a = 1;
+    ps.fields.buf_alloc_b = 1;
+    ps.fields.buf_alloc_c = 1;
+    ps.fields.buf_alloc_w = 1;
+
+    l_data64 = ps.value;
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL1_SCOM, l_data64),
+             "Failed to set Slave 1 control register");
 
     FAPI_INF("Initialize PBA Slave 2 ...");
     // Slave 2 (PGPE Boot).  This is a read/write slave.  Write gethering is