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| author | Brian Silver <bsilver@us.ibm.com> | 2016-09-07 10:45:29 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-08 15:49:09 -0400 |
| commit | 528c59f7dece8898cb9ea362a64b3327b7978d96 (patch) | |
| tree | c342472ebbbdd1388c93996bab680710753fe0d1 /src/import/chips/p9/procedures | |
| parent | 4837c147edef41e26a9b91339ca060f87c79ba76 (diff) | |
| download | talos-hostboot-528c59f7dece8898cb9ea362a64b3327b7978d96.tar.gz talos-hostboot-528c59f7dece8898cb9ea362a64b3327b7978d96.zip | |
Change DDR4 latency switch to always use MR0 A12
Change-Id: I05bef4eb2a55f2f2547aa4028e254ddcbd6920fe
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29322
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29326
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C index 26fec2e4f..bd0ff0e91 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C @@ -117,8 +117,9 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target) l_data.insertFromRight<TT::READ_LATENCY_OFFSET, TT::READ_LATENCY_OFFSET_LEN>(l_rlo); l_data.insertFromRight<TT::WRITE_LATENCY_OFFSET, TT::WRITE_LATENCY_OFFSET_LEN>(l_wlo); - // TODO RTC:160355 Need to check what mode to put this bit in if there are mixed 3DS/SDP DIMM - l_data.clearBit<TT::DDR4_LATENCY_SW>(); + // Always set this bit. It forces the PHY to use A12 when figuring out latency. This makes sense in + // all cases as A12 is 0 for non-3DS in MR0. + l_data.setBit<TT::DDR4_LATENCY_SW>(); FAPI_TRY( write_config1(i_target, l_data) ); |
