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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-09-07 13:28:51 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-09-13 09:59:21 -0400 |
| commit | 339026b470e3cd932dede11326f399a1a12ac3a7 (patch) | |
| tree | 380c6995438203c6a454adbe45d0db0cc369ca69 /src/import/chips/p9/procedures | |
| parent | 08c425e0639f5ddea4a6cd17077cac0105b925c7 (diff) | |
| download | talos-hostboot-339026b470e3cd932dede11326f399a1a12ac3a7.tar.gz talos-hostboot-339026b470e3cd932dede11326f399a1a12ac3a7.zip | |
Disabled Training Advance in sim
Change-Id: I7f52cc1675dd74bdba29a58ab46d1e1c3cd9a94d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45808
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45811
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C | 9 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 2 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C index cb431f5d1..ae3cd643c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C @@ -61,14 +61,19 @@ extern "C" { std::vector<fapi2::ReturnCode> l_fails; uint8_t l_cal_abort_on_error = i_abort_on_error; + uint8_t l_sim = 0; + FAPI_TRY( mss::is_simulation (l_sim) ); FAPI_INF("Start draminit training advance %s", mss::c_str(i_target)); // If there are no DIMMs installed, we don't need to bother. In fact, we can't as we didn't setup // attributes for the PHY, etc. - if (mss::count_dimm(i_target) == 0) + if (mss::count_dimm(i_target) == 0 || l_sim) { - FAPI_INF("... skipping draminit_training_adv %s - no DIMM ...", mss::c_str(i_target)); + FAPI_INF("... skipping draminit_training_adv %s... %s Dimms. %s SIM.", + mss::c_str(i_target), + mss::count_dimm(i_target) == 0 ? "Has no" : "Has", + l_sim ? "Is" : "Is not"); return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 645450a58..ff44acb98 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1986,7 +1986,6 @@ </description> <valueType>uint32</valueType> <initToZero></initToZero> - <default>0xEA0CA6C9</default> <enum>DEFAULT_PATTERN0 = 0xEA0C, DEFAULT_PATTERN1 = 0xA6C9</enum> <writeable/> <array>2</array> @@ -2013,7 +2012,6 @@ </description> <valueType>uint32</valueType> <initToZero></initToZero> - <default>0x13EC02FD</default> <enum>DEFAULT_PATTERN0 = 0x13EC, DEFAULT_PATTERN1 = 0x02FD</enum> <writeable/> <array>2</array> |
