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| author | LiuYangFan <shliuyf@cn.ibm.com> | 2016-03-11 03:04:06 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-01 11:49:17 -0400 |
| commit | 28d4903c629357bca036b0fecb3cf3fb8a6e16a9 (patch) | |
| tree | 6080589e2ac17680975363f9083cff5bf2dfd279 /src/import/chips/p9/procedures | |
| parent | d26d782b532cce24b36376ad7d4859be7d3cf526 (diff) | |
| download | talos-hostboot-28d4903c629357bca036b0fecb3cf3fb8a6e16a9.tar.gz talos-hostboot-28d4903c629357bca036b0fecb3cf3fb8a6e16a9.zip | |
L2 RAM procedures.
Changes included:
1. p9_ram_core: the class for base ramming operations (would reside in SBE)
2. p9_spr_name_map: the functions to map SPR name to SPR number (for Cronus use)
3. p9_ram_opcode: the procedure to implement ram an opcode
4. p9_ram_getspr: the procedure to implement get SPR value
5. p9_ram_putspr: the procedure to implement put SPR value
6. p9_ram_getreg: the procedure to implement get GPR/FPR/VSR value
7. p9_ram_putreg: the procedure to implement put GPR/FPR/VSR value
8. p9_ram_wrap: the eCMD wrapper to test the procedures
Change-Id: I34192e0527a61a48b9c1e69036a3411a1e3d9f6d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21933
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27571
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
22 files changed, 2002 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C new file mode 100644 index 000000000..6553c03f8 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -0,0 +1,581 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_core.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_core.C +/// @brief Class that implements the base ramming capability +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Sachin Gupta <sgupta2m@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_core.H> +#include "p9_quad_scom_addresses.H" +#include "p9_quad_scom_addresses_fld.H" + +// opcode for ramming +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; +const uint32_t OPCODE_MTSPR_FROM_GPR1_TO_SPRD = 0x7C3543A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR0 = 0x7C1542A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR1 = 0x7C3542A6; +const uint32_t OPCODE_MFSPR_FROM_SPR0_TO_GPR0 = 0x7C0002A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPR0 = 0x7C0003A6; +const uint32_t OPCODE_MFFPRD_FROM_FPR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MTFPRD_FROM_GPR0_TO_FPR0 = 0x7C000166; +const uint32_t OPCODE_MFVSRD_FROM_VSR0_TO_GPR0 = 0x7C000067; +const uint32_t OPCODE_MTVSRD_FROM_GPR0_TO_VSR0 = 0x7C000167; +const uint32_t OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0 = 0x7C000267; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0 = 0x7C010367; + +// poll count for check ram status +const uint32_t RAM_CORE_STAT_POLL_CNT = 10; + +// Scom register field +// TODO: replace the const with FLD macro define when it's ready +const uint32_t C_RAM_MODEREG_ENABLE = 0; +const uint32_t C_THREAD_INFO_VTID0_ACTIVE = 0; +const uint32_t C_RAM_CTRL_VTID = 0; +const uint32_t C_RAM_CTRL_VTID_LEN = 2; +const uint32_t C_RAM_CTRL_PREDECODE = 2; +const uint32_t C_RAM_CTRL_PREDECODE_LEN = 4; +const uint32_t C_RAM_CTRL_INSTRUCTION = 8; +const uint32_t C_RAM_CTRL_INSTRUCTION_LEN = 32; +const uint32_t C_RAM_STATUS_ACCESS_DURING_RECOVERY = 0; +const uint32_t C_RAM_STATUS_COMPLETION = 1; +const uint32_t C_RAM_STATUS_EXCEPTION = 2; +const uint32_t C_RAM_STATUS_LSU_EMPTY = 3; + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +RamCore::RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread) +{ + iv_target = i_target; + iv_thread = i_thread; + iv_ram_enable = false; + iv_ram_setup = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + iv_backup_buf0 = 0; + iv_backup_buf1 = 0; + iv_backup_buf2 = 0; +} + +RamCore::~RamCore() +{ + if(iv_ram_setup) + { + FAPI_ERR("RamCore Destructor error: Ram is still in active state!!!"); + } +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_setup() +{ + FAPI_INF("Start ram setup"); + fapi2::buffer<uint64_t> l_data = 0; + uint32_t l_opcode = 0; + bool l_thread_active = false; + + // set RAM_MODEREG Scom to enable RAM mode + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); + l_data.setBit<C_RAM_MODEREG_ENABLE>(); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + + // read THREAD_INFO Scom to check the thread is active for ramming + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_THREAD_INFO, l_data)); + FAPI_DBG("THREAD_INFO:%#lx", l_data()); + FAPI_TRY(l_data.extractToRight(l_thread_active, C_THREAD_INFO_VTID0_ACTIVE + iv_thread, 1)); + + FAPI_ASSERT(l_thread_active, + fapi2::P9_RAM_THREAD_INACTIVE_ERR() + .set_THREAD(iv_thread), + "Thread to perform ram is inactive"); + + iv_ram_enable = true; + + // backup registers SCR0/GPR0/GPR1 + //SCR0->iv_backup_buf0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf0)); + + //GPR0->iv_backup_buf1 + //1.setup SPRC to use SCRO as SPRD + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + //2.create mtsprd<gpr0> opcode, ram into thread to get GPR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR0 from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf1)); + + //GPR1->iv_backup_buf2 + //1.create mtsprd<gpr1> opcode, ram into thread to get GPR1 + l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get GPR1 from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf2)); + + iv_ram_setup = true; + +fapi_try_exit: + FAPI_INF("Exiting ram setup"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_cleanup() +{ + FAPI_INF("Start ram cleanup"); + uint32_t l_opcode = 0; + fapi2::buffer<uint64_t> l_data = 0; + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to cleanup ram without setup before"); + + // restore GPR1/GPR0/SCR0 + if(!iv_write_gpr0 && !iv_write_gpr1) + { + //iv_backup_buf2->GPR1 + //1.setup SPRC to use SCRO as SPRD + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + //2.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2)); + + //3.create mfsprd<gpr1> opcode, ram into thread to restore GPR1 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //iv_backup_buf1->GPR0 + //1.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1)); + + //2.create mfsprd<gpr0> opcode, ram into thread to restore GPR0 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); + } + // restore GPR0/SCR0 + else if(!iv_write_gpr0 && iv_write_gpr1) + { + //iv_backup_buf1->GPR0 + //1.setup SPRC to use SCRO as SPRD + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + //2.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1)); + + //3.create mfsprd<gpr0> opcode, ram into thread to restore GPR0 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); + } + // restore GPR1/SCR0 + else if(iv_write_gpr0 && !iv_write_gpr1) + { + //iv_backup_buf2->GPR1 + //1.setup SPRC to use SCRO as SPRD + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + //2.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2)); + + //3.create mfsprd<gpr0> opcode, ram into thread to restore GPR1 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); + } + // restore SCR0 + else + { + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); + } + + // set RAM_MODEREG Scom to clear RAM mode + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); + l_data.clearBit<C_RAM_MODEREG_ENABLE>(); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + + iv_ram_enable = false; + iv_ram_setup = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + +fapi_try_exit: + FAPI_INF("Exiting ram cleanup"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_opcode(const uint32_t i_opcode, const bool i_allow_mult) +{ + FAPI_INF("Start ram opcode"); + fapi2::buffer<uint64_t> l_data = 0; + uint8_t l_predecode = 0; + uint8_t l_poll_count = RAM_CORE_STAT_POLL_CNT; + bool l_is_load_store = false; + + // check the opcode for load/store + l_is_load_store = is_load_store(i_opcode); + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_enable, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to ram opcode without enable RAM mode before"); + + // write RAM_CTRL Scom for ramming the opcode + l_data.insertFromRight<C_RAM_CTRL_VTID, C_RAM_CTRL_VTID_LEN>(iv_thread); + l_predecode = gen_predecode(i_opcode); + l_data.insertFromRight<C_RAM_CTRL_PREDECODE, C_RAM_CTRL_PREDECODE_LEN>(l_predecode); + l_data.insertFromRight<C_RAM_CTRL_INSTRUCTION, C_RAM_CTRL_INSTRUCTION_LEN>(i_opcode); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_CTRL, l_data)); + + // poll RAM_STATUS_REG Scom for the completion + l_data.flush<0>(); + + while(1) + { + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_STATUS, l_data)); + + // attempting to ram during recovery + FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_ACCESS_DURING_RECOVERY>(), + fapi2::P9_RAM_STATUS_IN_RECOVERY_ERR(), + "Attempting to ram during recovery"); + + // exception or interrupt + FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_EXCEPTION>(), + fapi2::P9_RAM_STATUS_EXCEPTION_ERR(), + "Exception or interrupt happened during ramming"); + + // load/store opcode need to check LSU empty and PPC complete + if (l_is_load_store) + { + if(l_data.getBit<C_RAM_STATUS_COMPLETION>() && l_data.getBit<C_RAM_STATUS_LSU_EMPTY>()) + { + FAPI_DBG("ram_opcode:: RAM is done"); + break; + } + } + else + { + if(l_data.getBit<C_RAM_STATUS_COMPLETION>()) + { + FAPI_DBG("ram_opcode:: RAM is done"); + break; + } + } + + --l_poll_count; + + FAPI_ASSERT(l_poll_count > 0, + fapi2::P9_RAM_STATUS_POLL_THRESHOLD_ERR(), + "Timeout for ram to complete, poll count expired"); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + FAPI_INF("Exiting ram opcode"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +uint8_t RamCore::gen_predecode(const uint32_t i_opcode) +{ + //TODO: implement when the PC workbook is updated + return 0; +} + +//----------------------------------------------------------------------------------- +bool RamCore::is_load_store(const uint32_t i_opcode) +{ + //TODO: implement when the PC workbook is updated + return false; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, + fapi2::buffer<uint64_t>* o_buffer, const bool i_allow_mult) +{ + FAPI_INF("Start get register"); + uint32_t l_opcode = 0; + uint32_t l_spr_regnum_lo = 0; + uint32_t l_spr_regnum_hi = 0; + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to get register without setup before"); + + // get register value + if(i_type == REG_GPR) + { + //1.create mtsprd<i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_type == REG_SPR) + { + //1.create mfspr<gpr0, i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPR0_TO_GPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 11); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_type == REG_FPR) + { + //1.create mffprd<gpr0, i_reg_num>#SX=0 opcode, ram into thread + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_type == REG_VSR) + { + //1.create mfvsrd<gpr0, i_reg_num>#SX=1 opcode, ram into thread to get dw0 + l_opcode = OPCODE_MFVSRD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get VSR dw0 value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + + //4.create mfvrld<gpr0, i_reg_num>#SX=1 opcode, ram into thread to get dw1 + l_opcode = OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //5.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //6.get VSR dw1 value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[1])); + } + else + { + FAPI_ASSERT(false, + fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR() + .set_REGTYPE(i_type), + "Type of reg is not supported"); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + FAPI_INF("Exiting get register"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, + const fapi2::buffer<uint64_t>* i_buffer, const bool i_allow_mult) +{ + FAPI_INF("Start put register"); + uint32_t l_opcode = 0; + uint32_t l_spr_regnum_lo = 0; + uint32_t l_spr_regnum_hi = 0; + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to put register without setup before"); + + // put register value + if(i_type == REG_GPR) + { + //1.put GPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + if(i_reg_num == 0) + { + iv_write_gpr0 = true; + } + + if(i_reg_num == 1) + { + iv_write_gpr1 = true; + } + } + else if(i_type == REG_SPR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtspr<i_reg_num, gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 11); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_type == REG_FPR) + { + //1.put FPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtfprd<i_reg_num, gpr0>#TX=0 opcode, ram into thread + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_type == REG_VSR) + { + //1.put VSR dw1 value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[1])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.put VSR dw0 value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //4.create mfsprd<gpr1> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + l_opcode += (1 << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //5.create mtvsrdd<i_reg_num, gpr0, gpr1> opcode, ram into thread + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + FAPI_ASSERT(false, + fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR() + .set_REGTYPE(i_type), + "Type of reg is not supported"); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + FAPI_INF("Exiting put register"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H new file mode 100644 index 000000000..1e2d9d11b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H @@ -0,0 +1,145 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_core.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_core.H +/// @brief Class that implements the base ramming capability +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Sachin Gupta <sgupta2m@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_CORE_H_ +#define _P9_RAM_CORE_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- +// register access type +enum Enum_RegType +{ + REG_GPR, + REG_SPR, + REG_FPR, + REG_VSR +}; + + +class RamCore +{ + public: +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Constructor of the class that implements the base ramming capability +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +// + RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread); + +//----------------------------------------------------------------------------------- +/// @brief Destructor of the class that implements the base ramming capability +// + ~RamCore(); + +//----------------------------------------------------------------------------------- +/// @brief Enable RAM mode and backup the registers(SCR0/GPR0/GPR1) that will be destroyed later during ramming +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_setup(); + +//----------------------------------------------------------------------------------- +/// @brief Perform the ram and check ram is done +/// @param[in] i_opcode => opcode to ram +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_opcode(const uint32_t i_opcode, const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Clear RAM mode and restore the backup registers +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_cleanup(); + +//----------------------------------------------------------------------------------- +/// @brief Get a register value by ramming +/// @param[in] i_type => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register nubmer +/// @param[out] o_buffer => register value +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, fapi2::buffer<uint64_t>* o_buffer, + const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Put a register value by ramming +/// @param[in] i_type => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register nubmer +/// @param[in] i_buffer => register value +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, const fapi2::buffer<uint64_t>* i_buffer, + const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Generate predecode for the opcode to ramming +/// @param[in] i_opcode => opcode to ram +/// @return the predecode +// + uint8_t gen_predecode(const uint32_t i_opcode); + +//----------------------------------------------------------------------------------- +/// @brief Check the opcode is load/store or not +/// @param[in] i_opcode => opcode to ram +/// @return TRUE if it is load/store +// + bool is_load_store(const uint32_t i_opcode); + + private: + fapi2::Target<fapi2::TARGET_TYPE_CORE> iv_target; // core target + uint8_t iv_thread; // thread number + bool iv_ram_enable; // ram mode is enabled + bool iv_ram_setup; // ram mode is enabled and register backup is done + bool iv_write_gpr0; // putGPR0 operation is executed + bool iv_write_gpr1; // putGPR1 operatoin is executed + fapi2::buffer<uint64_t> iv_backup_buf0; // register backup data + fapi2::buffer<uint64_t> iv_backup_buf1; // register backup data + fapi2::buffer<uint64_t> iv_backup_buf2; // register backup data +}; + +#endif //_P9_RAM_CORE_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.mk b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.mk new file mode 100644 index 000000000..7951b533c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.mk @@ -0,0 +1,20 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_ram_core.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_ram_core +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.C new file mode 100644 index 000000000..e3f54bcb1 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.C @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_getreg.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_getreg.C +/// @brief Utility to implement Get Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_getreg.H> + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +fapi2::ReturnCode p9_ram_getreg(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const Enum_RegType i_type, + const uint32_t i_reg_num, + fapi2::buffer<uint64_t>* o_buffer) +{ + FAPI_INF("Start"); + // instantiate the basic RamCore class + RamCore ram(i_target, i_thread); + // call RamCore get_reg method + FAPI_TRY(ram.get_reg(i_type, i_reg_num, o_buffer)); + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H new file mode 100644 index 000000000..d17c884b3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_getreg.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_getreg.H +/// @brief Utility to implement Get Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_GETREG_H_ +#define _P9_RAM_GETREG_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> +#include <p9_ram_core.H> + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_ram_getreg_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const Enum_RegType i_type, + const uint32_t i_reg_num, + fapi2::buffer<uint64_t>* o_buffer); + + +extern "C" { +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +// @brief Implement Get Register(GPR/FPR/VSR) by ramming +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_type => register access type (REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register number +/// @param[out] o_buffer => register value +/// @return FAPI_RC_SUCCESS if the setup completes successfully +// + fapi2::ReturnCode p9_ram_getreg(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const Enum_RegType i_type, + const uint32_t i_reg_num, + fapi2::buffer<uint64_t>* o_buffer); + +} //extern"C" + +#endif //_P9_RAM_GETREG_H_ + + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.mk b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.mk new file mode 100644 index 000000000..43270d149 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.mk @@ -0,0 +1,22 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_ram_getreg.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_ram_getreg +libp9_ram_getreg_DEPLIBS += p9_ram_core +$(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C new file mode 100644 index 000000000..fc10a1fbf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_getspr.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_getspr.C +/// @brief Utility to implement Get SPR Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_getspr.H> + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +fapi2::ReturnCode p9_ram_getspr(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const std::string i_name, + fapi2::buffer<uint64_t>* o_buffer) +{ + FAPI_INF("Start"); + uint32_t spr_num = 0; + + // instantiate the basic RamCore class + RamCore ram(i_target, i_thread); + // map spr register name to number + FAPI_TRY(p9_spr_name_map_init()); + FAPI_TRY(p9_spr_name_map(i_name, false, spr_num)); + // call RamCore get_reg method + FAPI_TRY(ram.get_reg(REG_SPR, spr_num, o_buffer)); + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H new file mode 100644 index 000000000..e7e01cb2b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_getspr.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_getspr.H +/// @brief Utility to implement Get SPR Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_GETSPR_H_ +#define _P9_RAM_GETSPR_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> +#include <p9_ram_core.H> +#include <p9_spr_name_map.H> + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_ram_getspr_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const std::string i_name, + fapi2::buffer<uint64_t>* o_buffer); + + +extern "C" { +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Implement Get SPR Register by ramming +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_name => register name +/// @param[out] o_buffer => register value +/// @return FAPI_RC_SUCCESS if the setup completes successfully +// + fapi2::ReturnCode p9_ram_getspr(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const std::string i_name, + fapi2::buffer<uint64_t>* o_buffer); + +} //extern"C" + +#endif //_P9_RAM_GETSPR_H_ + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.mk b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.mk new file mode 100644 index 000000000..d108450c0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.mk @@ -0,0 +1,23 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_ram_getspr.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_ram_getspr +libp9_ram_getspr_DEPLIBS += p9_ram_core +libp9_ram_getspr_DEPLIBS += p9_spr_name_map +$(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.C new file mode 100644 index 000000000..c571bdfdb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.C @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_opcode.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_opcode.C +/// @brief Utility to implement ram an opcode +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_opcode.H> + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +fapi2::ReturnCode p9_ram_opcode(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const uint32_t i_opcode) +{ + FAPI_INF("Start"); + // instantiate the basic RamCore class + RamCore ram(i_target, i_thread); + // call RamCore ram_opcode method + FAPI_TRY(ram.ram_opcode(i_opcode)); + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.H new file mode 100644 index 000000000..f69541ffa --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_opcode.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_opcode.H +/// @brief Utility to implement ram an opcode +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_OPCODE_H_ +#define _P9_RAM_OPCODE_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> +#include <p9_ram_core.H> + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_ram_opcode_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const uint32_t i_opcode); + + +extern "C" { +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Ram an opcode into the thread +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_opcode => opcode +/// @return FAPI_RC_SUCCESS if the setup completes successfully +// + fapi2::ReturnCode p9_ram_opcode(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const uint32_t i_opcode); +} //extern"C" + +#endif //_P9_RAM_OPCODE_H_ + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.mk b/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.mk new file mode 100644 index 000000000..3808c7e3e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_opcode.mk @@ -0,0 +1,22 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_ram_opcode.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_ram_opcode +libp9_ram_opcode_DEPLIBS += p9_ram_core +$(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.C new file mode 100644 index 000000000..30cab8c31 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.C @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_putreg.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_putreg.C +/// @brief Utility to implement Put Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_putreg.H> + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +fapi2::ReturnCode p9_ram_putreg(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const Enum_RegType i_type, + const uint32_t i_reg_num, + const fapi2::buffer<uint64_t>* i_buffer) +{ + FAPI_INF("Start"); + // instantiate the basic RamCore class + RamCore ram(i_target, i_thread); + // call RamCore put_reg method + FAPI_TRY(ram.put_reg(i_type, i_reg_num, i_buffer)); + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H new file mode 100644 index 000000000..314df8706 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H @@ -0,0 +1,74 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_putreg.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_putreg.H +/// @brief Utility to implement Put Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_PUTREG_H_ +#define _P9_RAM_PUTREG_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> +#include <p9_ram_core.H> + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_ram_putreg_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const Enum_RegType i_type, + const uint32_t i_reg_num, + const fapi2::buffer<uint64_t>* i_buffer); + + +extern "C" { +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Implement Put Register(GPR/FPR/VSR) by ramming +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_type => register access type (REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register number +/// @param[in] i_buffer => register value +/// @return FAPI_RC_SUCCESS if the setup completes successfully +// + fapi2::ReturnCode p9_ram_putreg(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const Enum_RegType i_type, + const uint32_t i_reg_num, + const fapi2::buffer<uint64_t>* i_buffer); + +} //extern"C" + +#endif //_P9_RAM_PUTREG_H_ + + + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.mk b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.mk new file mode 100644 index 000000000..201313c8d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.mk @@ -0,0 +1,22 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_ram_putreg.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_ram_putreg +libp9_ram_putreg_DEPLIBS += p9_ram_core +$(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C new file mode 100644 index 000000000..922983879 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_putspr.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_putspr.C +/// @brief Utility to implement Put SPR Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_putspr.H> + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +fapi2::ReturnCode p9_ram_putspr(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const std::string i_name, + const fapi2::buffer<uint64_t>* i_buffer) +{ + FAPI_INF("Start"); + uint32_t spr_num = 0; + + // instantiate the basic RamCore class + RamCore ram(i_target, i_thread); + // map spr register name to number + FAPI_TRY(p9_spr_name_map_init()); + FAPI_TRY(p9_spr_name_map(i_name, true, spr_num)); + // call RamCore put_reg method + FAPI_TRY(ram.put_reg(REG_SPR, spr_num, i_buffer)); + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H new file mode 100644 index 000000000..c653c6534 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_ram_putspr.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_putspr.H +/// @brief Utility to implement Put SPR Register by ramming +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_PUTSPR_H_ +#define _P9_RAM_PUTSPR_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> +#include <p9_ram_core.H> +#include <p9_spr_name_map.H> + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_ram_putspr_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const std::string i_name, + const fapi2::buffer<uint64_t>* i_buffer); + + +extern "C" { +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Implement Put SPR Register by ramming +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_name => register name +/// @param[in] i_buffer => register value +/// @return FAPI_RC_SUCCESS if the setup completes successfully +// + fapi2::ReturnCode p9_ram_putspr(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_thread, + const std::string i_name, + const fapi2::buffer<uint64_t>* i_buffer); +} //extern"C" + +#endif //_P9_RAM_PUTSPR_H_ + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.mk b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.mk new file mode 100644 index 000000000..a91af5536 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.mk @@ -0,0 +1,23 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_ram_putspr.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_ram_putspr +libp9_ram_putspr_DEPLIBS += p9_ram_core +libp9_ram_putspr_DEPLIBS += p9_spr_name_map +$(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C new file mode 100644 index 000000000..5f66efa4c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_spr_name_map.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_spr_name_map.C +/// @brief Utility to map SPR name to SPR number +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_spr_name_map.H> + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +std::map<std::string, SPRMapEntry> spr_map; + +fapi2::ReturnCode p9_spr_name_map_init() +{ + FAPI_INF("Start SPR name map init"); + + FAPI_ASSERT(spr_map.empty(), + fapi2::P9_SPR_NAME_MAP_INIT_ERR(), + "SPR name map is not empty when initialization"); + + { + LIST_SPR_REG(DO_SPR_MAP) + } + +fapi_try_exit: + FAPI_INF("Exiting SPR name map init"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +bool p9_spr_name_map_check_flag(unsigned char i_reg_flag, bool i_write) +{ + unsigned char op_flag = ((unsigned char)i_write) + 0x1; + + return (bool)(i_reg_flag & op_flag); +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode p9_spr_name_map(const std::string i_name, const bool i_write, uint32_t& o_number) +{ + FAPI_INF("Start SPR name map"); + bool l_check_flag = false; + + if(spr_map.find(i_name) != spr_map.end()) + { + l_check_flag = p9_spr_name_map_check_flag(spr_map[i_name].flag, i_write); + + FAPI_ASSERT(l_check_flag, + fapi2::P9_SPR_INVALID_RW_MODE_ACCESS_ERR() + .set_REGNAME(i_name) + .set_RWFLAG(spr_map[i_name].flag), + "SPR RW mode check failed"); + + o_number = spr_map[i_name].number; + } + else + { + FAPI_ASSERT(false, + fapi2::P9_SPR_INVALID_NAME_ACCESS_ERR() + .set_REGNAME(i_name), + "SPR name is invalid"); + } + +fapi_try_exit: + FAPI_INF("Exiting SPR name map"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H new file mode 100644 index 000000000..0e9892109 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H @@ -0,0 +1,249 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/perv/p9_spr_name_map.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_spr_name_map.H +/// @brief Utility to map SPR name to SPR number +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : None (Cronus test only) +//----------------------------------------------------------------------------------- + +#ifndef _P9_SPR_NAME_MAP_H_ +#define _P9_SPR_NAME_MAP_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <map> +#include <fapi2.H> + +// Read-Write mode flag for each SPR register +const unsigned char FLAG_READ_ONLY = 0x1; +const unsigned char FLAG_WRITE_ONLY = 0x2; +const unsigned char FLAG_READ_WRITE = 0x3; + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- +typedef struct +{ + int number; + std::string spy_name; + // 0x1: read-only; 0x2: write-only; 0x3 read-write + unsigned char flag; +} SPRMapEntry; + + +// List all the SPR registers(name, number, spy_name, flag) +// Reference <P9 SPR List.xls> on the P9 care bringup wiki +// Note: +// when ram is enabled, the hardware forces HV=1 PR=0 +// current spy names are got from <P9 SPR List.xls> +#define LIST_SPR_REG(_op_)\ + _op_(XER ,1 , Reserved ,FLAG_READ_WRITE)\ + _op_(DSCR_RU ,3 , Reserved ,FLAG_READ_WRITE)\ + _op_(LR ,8 , Reserved ,FLAG_READ_WRITE)\ + _op_(CTR ,9 , Reserved ,FLAG_READ_WRITE)\ + _op_(UAMR ,13 , Reserved ,FLAG_READ_WRITE)\ + _op_(DSCR ,17 , Reserved ,FLAG_READ_WRITE)\ + _op_(DSISR ,18 , Reserved ,FLAG_READ_WRITE)\ + _op_(DAR ,19 , Reserved ,FLAG_READ_WRITE)\ + _op_(DEC ,22 , V_DEC ,FLAG_READ_WRITE)\ + _op_(SDR1 ,25 , Reserved ,FLAG_READ_WRITE)\ + _op_(SRR0 ,26 , Reserved ,FLAG_READ_WRITE)\ + _op_(SRR1 ,27 , Reserved ,FLAG_READ_WRITE)\ + _op_(CFAR ,28 , Reserved ,FLAG_READ_WRITE)\ + _op_(AMR ,29 , Reserved ,FLAG_READ_WRITE)\ + _op_(PIDR ,48 , Reserved ,FLAG_READ_WRITE)\ + _op_(IAMR ,61 , Reserved ,FLAG_READ_WRITE)\ + _op_(TFHAR ,128 , Reserved ,FLAG_READ_WRITE)\ + _op_(TFIAR ,129 , Reserved ,FLAG_READ_WRITE)\ + _op_(TEXASR ,130 , Reserved ,FLAG_READ_WRITE)\ + _op_(TEXASRU ,131 , Reserved ,FLAG_READ_WRITE)\ + _op_(CTRL_RU ,136 , CTRL ,FLAG_READ_ONLY )\ + _op_(TIDR ,144 , CTRL ,FLAG_READ_WRITE)\ + _op_(CTRL ,152 , Reserved ,FLAG_WRITE_ONLY)\ + _op_(FSCR ,153 , Reserved ,FLAG_READ_WRITE)\ + _op_(UAMOR ,157 , Reserved ,FLAG_READ_WRITE)\ + _op_(GSR ,158 , Reserved ,FLAG_READ_WRITE)\ + _op_(PSPB ,159 , V_PSPB ,FLAG_READ_WRITE)\ + _op_(DPDES ,176 , DPDES ,FLAG_READ_WRITE)\ + _op_(DAWR0 ,180 , Reserved ,FLAG_READ_WRITE)\ + _op_(RPR ,186 , Reserved ,FLAG_READ_WRITE)\ + _op_(CIABR ,187 , Reserved ,FLAG_READ_WRITE)\ + _op_(DAWRX0 ,188 , Reserved ,FLAG_READ_WRITE)\ + _op_(HFSCR ,190 , Reserved ,FLAG_READ_WRITE)\ + _op_(VRSAVE ,256 , Reserved ,FLAG_READ_WRITE)\ + _op_(SPRG3_RU ,259 , T_SPRG3 ,FLAG_READ_ONLY )\ + _op_(TB ,268 , L_TB ,FLAG_READ_ONLY )\ + _op_(TBU_RU ,269 , L_TBU ,FLAG_READ_ONLY )\ + _op_(SPRG0 ,272 , T_SPRG0 ,FLAG_READ_WRITE)\ + _op_(SPRG1 ,273 , T_SPRG1 ,FLAG_READ_WRITE)\ + _op_(SPRG2 ,274 , T_SPRG2 ,FLAG_READ_WRITE)\ + _op_(SPRG3 ,275 , T_SPRG3 ,FLAG_READ_WRITE)\ + _op_(SPRC ,276 , Reserved ,FLAG_READ_WRITE)\ + _op_(SPRD ,277 , Reserved ,FLAG_READ_WRITE)\ + _op_(CIR ,283 , CIR ,FLAG_READ_ONLY )\ + _op_(TBL ,284 , V_TBL ,FLAG_WRITE_ONLY)\ + _op_(TBLU ,285 , L_TBU ,FLAG_WRITE_ONLY)\ + _op_(TBU40 ,286 , L_TBU40 ,FLAG_WRITE_ONLY)\ + _op_(PVR ,287 , PVR ,FLAG_READ_ONLY )\ + _op_(HSPRG0 ,304 , T_HSPRG0 ,FLAG_READ_WRITE)\ + _op_(HSPRG1 ,305 , T_HSPRG1 ,FLAG_READ_WRITE)\ + _op_(HDSISR ,306 , Reserved ,FLAG_READ_WRITE)\ + _op_(HDAR ,307 , Reserved ,FLAG_READ_WRITE)\ + _op_(SPURR ,308 , V_SPURR ,FLAG_READ_WRITE)\ + _op_(PURR ,309 , V_PURR ,FLAG_READ_WRITE)\ + _op_(HDEC ,310 , L_HDEC ,FLAG_READ_WRITE)\ + _op_(RMOR ,312 , Reserved ,FLAG_READ_WRITE)\ + _op_(HRMOR ,313 , Reserved ,FLAG_READ_WRITE)\ + _op_(HSRR0 ,314 , Reserved ,FLAG_READ_WRITE)\ + _op_(HSRR1 ,315 , Reserved ,FLAG_READ_WRITE)\ + _op_(TFMR ,317 , V_TFMR ,FLAG_READ_WRITE)\ + _op_(LPCR ,318 , Reserved ,FLAG_READ_WRITE)\ + _op_(LPIDR ,319 , Reserved ,FLAG_READ_WRITE)\ + _op_(HMER ,336 , V_HMER ,FLAG_READ_WRITE)\ + _op_(HMEER ,337 , HMEER ,FLAG_READ_WRITE)\ + _op_(PCR ,338 , L_PCR ,FLAG_READ_WRITE)\ + _op_(HEIR ,339 , Reserved ,FLAG_READ_WRITE)\ + _op_(AMOR ,349 , Reserved ,FLAG_READ_WRITE)\ + _op_(TIR ,446 , TIR ,FLAG_READ_ONLY )\ + _op_(PTCR ,464 , Reserved ,FLAG_READ_WRITE)\ + _op_(USPRG0 ,496 , Reserved ,FLAG_READ_WRITE)\ + _op_(USPRG1 ,497 , Reserved ,FLAG_READ_WRITE)\ + _op_(UDAR ,499 , Reserved ,FLAG_READ_WRITE)\ + _op_(SEIDR ,504 , Reserved ,FLAG_READ_WRITE)\ + _op_(URMOR ,505 , Reserved ,FLAG_READ_WRITE)\ + _op_(USRR0 ,506 , Reserved ,FLAG_READ_WRITE)\ + _op_(USRR1 ,507 , Reserved ,FLAG_READ_WRITE)\ + _op_(UEIR ,509 , Reserved ,FLAG_READ_WRITE)\ + _op_(ACMCR ,510 , Reserved ,FLAG_READ_WRITE)\ + _op_(SEIDBAR ,511 , Reserved ,FLAG_READ_WRITE)\ + _op_(SIER_RU ,768 , Reserved ,FLAG_READ_ONLY )\ + _op_(MMCR2_RU ,769 , Reserved ,FLAG_READ_ONLY )\ + _op_(MMCRA_RU ,770 , Reserved ,FLAG_READ_ONLY )\ + _op_(PMC1_RU ,771 , Reserved ,FLAG_READ_ONLY )\ + _op_(PMC2_RU ,772 , Reserved ,FLAG_READ_ONLY )\ + _op_(PMC3_RU ,773 , Reserved ,FLAG_READ_ONLY )\ + _op_(PMC4_RU ,774 , Reserved ,FLAG_READ_ONLY )\ + _op_(PMC5_RU ,775 , Reserved ,FLAG_READ_ONLY )\ + _op_(PMC6_RU ,776 , Reserved ,FLAG_READ_ONLY )\ + _op_(MMCR0_RU ,779 , Reserved ,FLAG_READ_ONLY )\ + _op_(SIAR_RU ,780 , Reserved ,FLAG_READ_ONLY )\ + _op_(SDAR_RU ,781 , Reserved ,FLAG_READ_ONLY )\ + _op_(MMCR1_RU ,782 , Reserved ,FLAG_READ_ONLY )\ + _op_(SIER ,784 , T_SIER ,FLAG_READ_WRITE)\ + _op_(MMCR2 ,785 , T_MMCR2 ,FLAG_READ_WRITE)\ + _op_(MMCRA ,786 , T_MMCRA ,FLAG_READ_WRITE)\ + _op_(PMC1 ,787 , T_PMC1 ,FLAG_READ_WRITE)\ + _op_(PMC2 ,788 , T_PMC2 ,FLAG_READ_WRITE)\ + _op_(PMC3 ,789 , T_PMC3 ,FLAG_READ_WRITE)\ + _op_(PMC4 ,790 , T_PMC4 ,FLAG_READ_WRITE)\ + _op_(PMC5 ,791 , T_PMC5 ,FLAG_READ_WRITE)\ + _op_(PMC6 ,792 , T_PMC6 ,FLAG_READ_WRITE)\ + _op_(MMCR0 ,795 , T_MMCR0 ,FLAG_READ_WRITE)\ + _op_(SIAR ,796 , Reserved ,FLAG_READ_WRITE)\ + _op_(SDAR ,797 , Reserved ,FLAG_READ_WRITE)\ + _op_(MMCR1 ,798 , T_MMCR1 ,FLAG_READ_WRITE)\ + _op_(IMC ,799 , Reserved ,FLAG_READ_WRITE)\ + _op_(BESCRS ,800 , Reserved ,FLAG_READ_WRITE)\ + _op_(BESCRSU ,801 , Reserved ,FLAG_READ_WRITE)\ + _op_(BESCRR ,802 , Reserved ,FLAG_READ_WRITE)\ + _op_(BESCRRU ,803 , Reserved ,FLAG_READ_WRITE)\ + _op_(EBBHR ,804 , Reserved ,FLAG_READ_WRITE)\ + _op_(EBBRR ,805 , Reserved ,FLAG_READ_WRITE)\ + _op_(BESCR ,806 , Reserved ,FLAG_READ_WRITE)\ + _op_(LMRR ,813 , Reserved ,FLAG_READ_WRITE)\ + _op_(LMSER ,814 , Reserved ,FLAG_READ_WRITE)\ + _op_(TAR ,815 , Reserved ,FLAG_READ_WRITE)\ + _op_(ASDR ,816 , Reserved ,FLAG_READ_WRITE)\ + _op_(PSSCR_SU ,823 , Reserved ,FLAG_READ_WRITE)\ + _op_(IC ,848 , T_IC ,FLAG_READ_WRITE)\ + _op_(VTB ,849 , L_VTB ,FLAG_READ_WRITE)\ + _op_(LDBAR ,850 , L_LDBAR ,FLAG_READ_WRITE)\ + _op_(MMCRC ,851 , MMCRC ,FLAG_READ_WRITE)\ + _op_(PMSR ,853 , PMSR ,FLAG_READ_ONLY )\ + _op_(PMMAR ,854 , PMMAR ,FLAG_READ_WRITE)\ + _op_(PSSCR ,855 , V_PSSCR ,FLAG_READ_WRITE)\ + _op_(L2QOSR ,861 , L_PMMAR ,FLAG_WRITE_ONLY)\ + _op_(WORC ,863 , Reserved ,FLAG_READ_WRITE)\ + _op_(TRIG0 ,880 , Reserved ,FLAG_WRITE_ONLY)\ + _op_(TRIG1 ,881 , Reserved ,FLAG_WRITE_ONLY)\ + _op_(TRIG2 ,882 , Reserved ,FLAG_WRITE_ONLY)\ + _op_(PMCR ,884 , PMCR ,FLAG_READ_WRITE)\ + _op_(RWMR ,885 , PWMR ,FLAG_READ_WRITE)\ + _op_(WORT ,895 , Reserved ,FLAG_READ_WRITE)\ + _op_(PPR ,896 , Reserved ,FLAG_READ_WRITE)\ + _op_(PPR32 ,898 , Reserved ,FLAG_READ_WRITE)\ + _op_(TSCR ,921 , Reserved ,FLAG_READ_WRITE)\ + _op_(TTR ,922 , Reserved ,FLAG_READ_WRITE)\ + _op_(TRACE ,1006, TRACE ,FLAG_WRITE_ONLY)\ + _op_(HID ,1008, HID ,FLAG_READ_WRITE)\ + _op_(PIR ,1023, PIR ,FLAG_WRITE_ONLY) + +#define DO_SPR_MAP(in_name, in_number, in_spy_name, in_flag)\ + SPRMapEntry entry##in_name; \ + entry##in_name.number = in_number; \ + entry##in_name.spy_name = #in_spy_name; \ + entry##in_name.flag = in_flag; \ + spr_map[#in_name] = entry##in_name; + +//----------------------------------------------------------------------------------- +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_spr_name_map_FP_t) (const std::string i_name, const bool i_write, uint32_t& o_number); + + +extern "C" { +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Initial the map between SPR name and SPR number +/// @return FAPI_RC_SUCCESS if the mapping completes successfully +// + fapi2::ReturnCode p9_spr_name_map_init(); + + +//----------------------------------------------------------------------------------- +/// @brief Check read-write mode for a SPR register access +/// @param[in] i_reg_flag => read-write mode of the SPR register +/// @param[in] i_write => indicate write/read SPR +/// @return TRUE if the check completes successfully +// + bool p9_spr_name_map_check_flag(unsigned char i_reg_flag, bool i_write); + +//----------------------------------------------------------------------------------- +/// @brief Map SPR name to SPR number +/// @param[in] i_name => SPR name +/// @param[in] i_write => indicate write/read SPR +/// @param[out] o_number => SPR number +/// @return FAPI_RC_SUCCESS if the mapping completes successfully +// + fapi2::ReturnCode p9_spr_name_map(const std::string i_name, + const bool i_write, + uint32_t& o_number); +} //extern"C" + +#endif //_P9_SPR_NAME_MAP_H_ + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.mk b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.mk new file mode 100644 index 000000000..b9e29e6ab --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.mk @@ -0,0 +1,21 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: chips/p9/procedures/hwp/perv/p9_spr_name_map.mk $ +# +# IBM CONFIDENTIAL +# +# EKB Project +# +# COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_spr_name_map +$(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml new file mode 100644 index 000000000..eeb58521a --- /dev/null +++ b/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml @@ -0,0 +1,127 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: chips/p9/procedures/xml/error_info/p9_ram_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- EKB Project --> +<!-- --> +<!-- COPYRIGHT 2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for p9 ram procedures --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_SPR_NAME_MAP_INIT_ERR</rc> + <description> + SPR name map is not empty while try to initialize + </description> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_SPR_INVALID_RW_MODE_ACCESS_ERR</rc> + <description> + Illegal SPR read/write mode access + </description> + <ffdc>REGNAME</ffdc> + <ffdc>RWFLAG</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_SPR_INVALID_NAME_ACCESS_ERR</rc> + <description> + Illegal SPR name access + </description> + <ffdc>REGNAME</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_RAM_NOT_SETUP_ERR</rc> + <description> + RAM is not setup as active before doing ram or cleanup + </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_RAM_THREAD_INACTIVE_ERR</rc> + <description> + The thread to perform ramming is not active + </description> + <ffdc>THREAD</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_RAM_STATUS_IN_RECOVERY_ERR</rc> + <description> + Attempt to perform ramming during recovery + </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_RAM_STATUS_EXCEPTION_ERR</rc> + <description> + Exception or interrupt happened during ramming + </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_RAM_STATUS_POLL_THRESHOLD_ERR</rc> + <description> + Polling for ram done reached threshold + </description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9_RAM_INVALID_REG_TYPE_ACCESS_ERR</rc> + <description> + Illegal reg type access + </description> + <ffdc>REGTYPE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> + |
