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| author | Brian Silver <bsilver@us.ibm.com> | 2016-08-17 08:29:44 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-10-25 14:27:31 -0400 |
| commit | 244cda98f3c221e9b09e791957646b9177c307be (patch) | |
| tree | 043eb60d2c50b076f5ed05f7b8a60f6ee9b25d18 /src/import/chips/p9/procedures | |
| parent | 625e85ec0d587836eba8978a0922fb29b7e61ba4 (diff) | |
| download | talos-hostboot-244cda98f3c221e9b09e791957646b9177c307be.tar.gz talos-hostboot-244cda98f3c221e9b09e791957646b9177c307be.zip | |
Implement MRW attributes; dram_clks, db_util, 2n_mode
ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS
ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL
ATTR_MSS_MRW_DRAM_2N_MODE
TSYS_ADR, TSYS_DATA moved the MT VPD
GPO, RLO, WLO moved to the MT VPD
Update hb defaults
Update unit test to catch the 2N mode MRW changes
Change-Id: Ia16293495941fe4dd190196c00724ff69593303a
Original-Change-Id: I3d998c70d30df978062ce923096ba741d597782e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28383
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31754
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C index 48285cb3f..ba7039e82 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C @@ -62,27 +62,24 @@ extern "C" /// fapi2::ReturnCode p9_mss_utils_to_throttle( const fapi2::Target<TARGET_TYPE_MCS>& i_target ) { - std::vector<uint8_t> l_databus_util(mss::PORTS_PER_MCS, 0); + uint32_t l_databus_util = 0; std::vector<uint32_t> l_throttled_cmds(mss::PORTS_PER_MCS, 0); uint32_t l_dram_clocks = 0; FAPI_TRY( mss::mrw_mem_m_dram_clocks(l_dram_clocks) ); - // TK - Who sets this attribute? OCC? Not set in eff_config for p8 - AAM - // If set by OCC can they just pass in value as a parameter? - AAM - FAPI_TRY( mss::databus_util( i_target, l_databus_util.data()) ); + FAPI_TRY( mss::mrw_max_dram_databus_util(l_databus_util) ); for( const auto& l_mca : mss::find_targets<TARGET_TYPE_MCA>(i_target) ) { const auto l_port_num = mss::index( l_mca ); - FAPI_INF( "MRW dram clock window: %d, databus utilization[%d]: %d", + FAPI_INF( "MRW dram clock window: %d, databus utilization: %d", l_dram_clocks, - l_port_num, - l_databus_util[l_port_num] ); + l_databus_util ); // Calculate programmable N address operations within M dram clock window - l_throttled_cmds[l_port_num] = mss::throttled_cmds( l_databus_util[l_port_num], l_dram_clocks ); + l_throttled_cmds[l_port_num] = mss::throttled_cmds( l_databus_util, l_dram_clocks ); FAPI_INF( "Calculated N commands per port [%d] = %d", l_port_num, |
