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| author | Andre A. Marin <aamarin@us.ibm.com> | 2019-05-09 10:08:25 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-13 12:19:06 -0500 |
| commit | f83005325604106a140cfc3f3673165a36b93b7e (patch) | |
| tree | 9e00e6e54327c648c296b9e4ae5a9b3e75f3fbce /src/import/chips/p9/procedures/xml | |
| parent | b952df368d4204b91f6374036051cfd99f1834d6 (diff) | |
| download | talos-hostboot-f83005325604106a140cfc3f3673165a36b93b7e.tar.gz talos-hostboot-f83005325604106a140cfc3f3673165a36b93b7e.zip | |
Added Nimbus NDVDIMM specific DIMM slot attribute
Change-Id: I4ae692f931ebaac275cd3a66783a5fceb2d6894f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77179
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: TSUNG K YEUNG <tyeung@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77193
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rwxr-xr-x | src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 078f79284..ae6bbb47e 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -24,6 +24,22 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> + <attribute> + <id>ATTR_MSS_MRW_NVDIMM_SLOT_POSITION</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + The position of a dimm is based on which mca it is + associated with and which drop behind that mca, with + 16 dimms possible per processor socket. The formula is: + [processor position with no gaps, i.e. 0,1,2,3]*16 + + [mca position on this processor * 2] + [dimm location behind this mca] + </description> + <valueType>uint8</valueType> + <default>0xFF</default> + <platInit/> + <mrwHide/> + <mssAccessorName>mrw_nvdimm_slot_position</mssAccessorName> + </attribute> <attribute> <id>ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG</id> |
