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| author | Greg Still <stillgs@us.ibm.com> | 2018-03-09 16:43:33 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-15 15:14:14 -0400 |
| commit | cbcd27d3a6292e709ab4b22811364b1abc47441a (patch) | |
| tree | a1d2dc80a16d24d465383a3ff38e740b625adb75 /src/import/chips/p9/procedures/xml | |
| parent | b1e597ec9bdb0df07fc3e492d208fdc8f46fed64 (diff) | |
| download | talos-hostboot-cbcd27d3a6292e709ab4b22811364b1abc47441a.tar.gz talos-hostboot-cbcd27d3a6292e709ab4b22811364b1abc47441a.zip | |
PM: p9_setup_evid steps voltage to avoid Fleetwood VRM limitations
- use the present value of ATTR_EXT_VRM_STEPSIZE (used by PGPE for Pstate
movement) to step the the boot voltage setup during istep 8. This attribute
defaults to 50mV.
- Done only for rails attached via AVSBus
Key_Cronus_Test=PM_REGRESS
Change-Id: I63feb361323246c8b92f1e96dc41f8fc19bd0912
CQ: SW420343
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55386
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55395
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index 647a387e1..4c21650ce 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -31,14 +31,15 @@ <attribute> <id>ATTR_EXTERNAL_VRM_STEPSIZE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <!-- <<<<<<< PROC_CHIP POSSIBLE --> <description> Step size (binary in microvolts) to take upon external VRM voltage transitions. The value set here must take into account where internal VRMs are enabled or not as, when they are enabled, the step size must account for the tracking (eg PFET strength recalculation) for the step. + Firmware provides a default value of 50mV if this attribute is zero. Consumer: p9_pstate_parameter_block -> + p9_setup_evid Pstate Parameter Block (PSPB) for PGPE Provided by the Machine Readable Workbook after system characterization. @@ -50,14 +51,12 @@ <attribute> <id>ATTR_EXTERNAL_VRM_STEPDELAY</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <!-- <<<<<<< PROC_CHIP POSSIBLE --> <description> - Step delay (binary in microseconds) after a voltage change - - Consumer: p9_pstate_parameter_block -> - Pstate Parameter Block (PSPB) for PGPE - - Provided by the Machine Readable Workbook after system characterization. + This attribute is deprecated and is not consumed. See + ATTR_EXTERNAL_VRM_TRANSITION_START_NS, + ATTR_EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US, + ATTR_EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US, and + ATTR_EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS </description> <valueType>uint32</valueType> <platInit/> |
