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| author | Joe McGill <jmcgill@us.ibm.com> | 2019-05-30 22:44:31 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-05 22:15:39 -0500 |
| commit | 4b03b01b34bd1d2a1d4cbfd5cbcb162dc3664067 (patch) | |
| tree | 4350867bc29475478e699c9c75b32a0338f4cf58 /src/import/chips/p9/procedures/xml | |
| parent | 3f6ff0a8bddfd7d9b916239707e04ff52be4c8fb (diff) | |
| download | talos-hostboot-4b03b01b34bd1d2a1d4cbfd5cbcb162dc3664067.tar.gz talos-hostboot-4b03b01b34bd1d2a1d4cbfd5cbcb162dc3664067.zip | |
p9.filter.pll.scan.initfile -- update CP filter config for p9a
CP refclock input is expected to be 100MHz for p9a
Change-Id: I664dd9122f260fe1abb25c01c813ffadc289f460
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78117
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78121
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index f61c96f15..b994443f8 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -116,6 +116,23 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_CP_FILTER_100MHZ</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True where CP refclock is expected to be 100 MHz + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_DD1_FBC_AND_ALINK</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> |
