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author | Jacob Harvey <jlharvey@us.ibm.com> | 2016-12-12 14:33:41 -0600 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-01-03 14:07:59 -0500 |
commit | 2ed96daee929460c101fbd1051045502268c66e2 (patch) | |
tree | 42a7cecc54cd079d0fd0b7ed39a5e711a455c356 /src/import/chips/p9/procedures/xml | |
parent | 3edc690745d300c5bd55e4bcad823c62883cfd6a (diff) | |
download | talos-hostboot-2ed96daee929460c101fbd1051045502268c66e2.tar.gz talos-hostboot-2ed96daee929460c101fbd1051045502268c66e2.zip |
Move MRS attributes to eff_config to calc LRDIMMs
Change-Id: Ie2b6d187d67f8bc7ed975e7627fd31ff343e8969
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33774
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33781
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 13840e996..8b0385386 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -2221,6 +2221,52 @@ </attribute> <attribute> + <id>ATTR_EFF_DRAM_RTT_NOM</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + RTT_NOM value read to be programmed into MRS02 + For RDIMMS, this is based off of the VPD + For LRDIMMS, this comes from the SPD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 4</array> + <mssAccessorName>eff_dram_rtt_nom</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EFF_DRAM_RTT_WR</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + RTT_WR value read to be programmed into MRS02 + For RDIMMS, this is based off of the VPD + For LRDIMMS, this comes from the SPD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 4</array> + <mssAccessorName>eff_dram_rtt_wr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EFF_DRAM_RTT_PARK</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + RTT_PARK value read to be programmed into MRS05 + For RDIMMS, this is based off of the VPD + For LRDIMMS, this comes from the SPD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable /> + <array> 2 2 4</array> + <mssAccessorName>eff_dram_rtt_park</mssAccessorName> + </attribute> + + + <attribute> <id>ATTR_EFF_DIMM_DDR4_BC00</id> <targetType>TARGET_TYPE_MCS</targetType> <description>F0BCW00 Host Interface DQ RTT_NOM Control</description> |