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| author | Brian Silver <bsilver@us.ibm.com> | 2016-09-03 21:19:03 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-09-12 13:50:55 -0400 |
| commit | 0f29aac88c66f0e5c36756b8fdafe2bf2fbd3dd1 (patch) | |
| tree | 70d476c4074efa3ffcf323cc975d4738197338dc /src/import/chips/p9/procedures/xml | |
| parent | 5a162834cb4e2fce195c169ece26eef87577f17f (diff) | |
| download | talos-hostboot-0f29aac88c66f0e5c36756b8fdafe2bf2fbd3dd1.tar.gz talos-hostboot-0f29aac88c66f0e5c36756b8fdafe2bf2fbd3dd1.zip | |
Add VPD decode and attributes for DQ and CKE maps
Fix include path in raw_card.C
Change-Id: I1d02ed92d11667e639e832be72a86cdec5035a90
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29222
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29224
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml | 45 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml | 42 |
2 files changed, 87 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml new file mode 100644 index 000000000..5c7de669c --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml @@ -0,0 +1,45 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + <attribute> + <id>ATTR_MSS_VPD_CKE_MAP</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable signal to its respective rank. + There are 8 bits, but only 4 are currently used + [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] + E.g. 0x80 -> 0b10000000, which means DIMM0 CKE0 is mapped to that rank. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits></mssUnits> + <mssBlobStart>0</mssBlobStart> + <mssBlobLength>16</mssBlobLength> + <mssAccessorName>vpd_cke_map</mssAccessorName> + <array>2 2 4</array> + </attribute> + +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml new file mode 100644 index 000000000..6dab3219e --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml @@ -0,0 +1,42 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + <attribute> + <id>ATTR_MSS_VPD_DQ_MAP</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + [PORT][Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits></mssUnits> + <mssBlobStart>0</mssBlobStart> + <mssBlobLength>144</mssBlobLength> + <mssAccessorName>vpd_dq_map</mssAccessorName> + <array>2 72</array> + </attribute> + +</attributes> |
