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| author | Yue Du <daviddu@us.ibm.com> | 2015-12-04 15:37:19 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-08-20 09:55:45 -0400 |
| commit | 2de6dae30f6d1fcb5b16de29babff1042f9cbfcb (patch) | |
| tree | 5d71cb66f6a54e0c1eb830dfcf7424d4bc8fd97c /src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml | |
| parent | dbd18ce098b79068017fec205005a75d0e8b57e0 (diff) | |
| download | talos-hostboot-2de6dae30f6d1fcb5b16de29babff1042f9cbfcb.tar.gz talos-hostboot-2de6dae30f6d1fcb5b16de29babff1042f9cbfcb.zip | |
HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34
Change-Id: I4aa66157d54b4c00026f93db96d3069c46516ff2
Original-Change-Id: Ia88b64463b0b911aa0882db20b85eda7a30571d6
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22225
Tested-by: Jenkins Server
Tested-by: PPE CI
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44846
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml index c8a6c3b11..e5bdc5ed3 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml @@ -55,4 +55,64 @@ </gard> </hwpError> <!-- ********************************************************************* --> + <hwpError> + <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc> + <description> + dpll clock start timed out. + </description> + <ffdc>EQCLKSTAT</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> + <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc> + <description> + anep clock start timed out. + </description> + <ffdc>EQCLKSTAT</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childNumber>EX_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> + </hwpError> + <!-- ********************************************************************* --> </hwpErrors> |
