L2 HWP -- p9_setup_bars

p9_setup_bars
  initial relase -- program FSP/PSI/NPU BARs & configure MCD

nest_attributes
proc_setup_bars_attributes
  adjust scope of BAR base address attributes from chip->system
  change to reflect offset from base of chip address range, rather than
  absolute address

p9_fbc_utils
  modify p9_fbc_utils_get_chip_base_address() to output base of each on
  chip region, consider policy affecting placement of mirrrored memory

p9_mss_eff_grouping
p9_sbe_load_bootloader
p9_sbe_mcs_setup
  adapt to p9_fbc_utils_get_chip_base_address() changes

p9_sbe_scominit
  adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes
  add placeholder for FIR register initialization

p9_pcie_config
  adapt to p9_fbc_utils_get_chip_base_address() / attribute scope changes
  skip programming of INT resources

Change-Id: I62e1766fbe8366168cc3f1b9b43c64f48659aec0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27841
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27850
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 226 insertions, 44 deletions

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
index a7a27813e..dfdd54f99 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
@@ -26,9 +26,9 @@
 <attributes>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id>
+    <id>ATTR_PROC_FSP_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>PSI Bridge BAR enable
+    <description>FSP BAR enable
       creator: platform
       consumer: p9_setup_bars
       firmware notes: none
@@ -40,15 +40,15 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>PSI Bridge BAR base address value
+    <id>ATTR_PROC_FSP_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>FSP BAR
       creator: platform
       consumer: p9_setup_bars
       firmware notes:
-        64-bit address representing BAR RA
-        NOTE: BAR register covers RA 8:43
-        NOTE: Implied size of 1MB
+        Defines range mapped for FSP MMIO
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- RA bits 22:43
     </description>
     <valueType>uint64</valueType>
     <platInit/>
@@ -56,9 +56,59 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_FSP_BAR_ENABLE</id>
+    <id>ATTR_PROC_FSP_BAR_SIZE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>FSP BAR size value
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+        4_GB = 0xFFFFFC00FFFFFFFF,
+        2_GB = 0xFFFFFC007FFFFFFF,
+        1_GB = 0xFFFFFC003FFFFFFF,
+      512_MB = 0xFFFFFC001FFFFFFF,
+      256_MB = 0xFFFFFC000FFFFFFF,
+      128_MB = 0xFFFFFC0007FFFFFF,
+       64_MB = 0xFFFFFC0003FFFFFF,
+       32_MB = 0xFFFFFC0001FFFFFF,
+       16_MB = 0xFFFFFC0000FFFFFF,
+        8_MB = 0xFFFFFC00007FFFFF,
+        4_MB = 0xFFFFFC00003FFFFF,
+        2_MB = 0xFFFFFC00001FFFFF,
+        1_MB = 0xFFFFFC00000FFFFF
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>FSP MMIO mask size value
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        AND mask applied to RA 32:35 when transmitting address to FSP
+        NOTE: RA 8:31 are always replaced with zero
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+        4_GB = 0x00F0000000000000,
+        2_GB = 0x0070000000000000,
+        1_GB = 0x0030000000000000,
+      512_MB = 0x0010000000000000,
+      256_MB = 0x0000000000000000
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>FSP BAR enable
+    <description>NPU PHY0 (stack0) BAR enable
       creator: platform
       consumer: p9_setup_bars
       firmware notes: none
@@ -70,14 +120,16 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>FSP BAR base address value
+    <id>ATTR_PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU PHY0 (stack0) BAR
       creator: platform
       consumer: p9_setup_bars
       firmware notes:
-        64-bit address representing BAR RA
-        NOTE: BAR register covers RA 8:43
+        Defines 2MB range (size implied) mapped to PHY0 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- RA bits 22:42
+        (excludes system/memory select/group/chip fields)
     </description>
     <valueType>uint64</valueType>
     <platInit/>
@@ -85,55 +137,185 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_FSP_BAR_SIZE</id>
+    <id>ATTR_PROC_NPU_PHY1_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>FSP BAR size value
+    <description>NPU PHY1 (stack1) BAR enable
       creator: platform
       consumer: p9_setup_bars
       firmware notes: none
     </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU PHY1 (stack1) BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 2MB range (size implied) mapped to PHY1 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- RA bits 22:42
+        (excludes system/memory select/group/chip fields)
+    </description>
     <valueType>uint64</valueType>
-    <enum>
-        4_GB = 0x0000000100000000,
-        2_GB = 0x0000000080000000,
-        1_GB = 0x0000000040000000,
-      512_MB = 0x0000000020000000,
-      256_MB = 0x0000000010000000,
-      128_MB = 0x0000000008000000,
-       64_MB = 0x0000000004000000,
-       32_MB = 0x0000000002000000,
-       16_MB = 0x0000000001000000,
-        8_MB = 0x0000000000800000,
-        4_MB = 0x0000000000400000,
-        2_MB = 0x0000000000200000,
-        1_MB = 0x0000000000100000
-    </enum>
     <platInit/>
     <persistRuntime/>
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id>
+    <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU MMIO (stack2) BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to all NPU registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- RA bits 22:39
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>FSP MMIO mask size value
+    <description>NPU MMIO (stack2) BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>PSI Bridge BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* --> 
+  <attribute>
+    <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>PSI Bridge BAR base address offset
       creator: platform
       consumer: p9_setup_bars
       firmware notes:
-        AND mask applied to RA 32:35 when transmitting address to FSP
-        NOTE: RA 8:31 are always replaced with zero
+        Defines 1MB range (size implied) mapped for PSI host-bridge
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- RA bits 22:43
+        (excludes system/memory select/group/chip fields)
     </description>
     <valueType>uint64</valueType>
-    <enum>
-        4_GB = 0x0000000100000000,
-        2_GB = 0x0000000080000000,
-        1_GB = 0x0000000040000000,
-      512_MB = 0x0000000020000000,
-      256_MB = 0x0000000010000000
-    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NX_RNG_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NX RNG BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NX RNG BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 8KB range (size implied) mapped for NX RNG function
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- RA bits 22:51
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NX_RNG_FAILED_INT_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Enable optional post of interrupt when both NX RNG noise
+                sources have failed
+      creator: platform
+      consumer: p9_rng_init_phase2
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NX_RNG_FAILED_INT_ADDR</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Address used to post interrupt when both NX RNG noise
+                 sources have failed
+      creator: platform
+      consumer: p9_rng_init_phase2
+      firmware notes:
+        64-bit address representing RA
+        NOTE: register covers RA 8:51
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NX_RNG_BIST_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Enable NX RNG BIST
+      creator: platform
+      consumer: p9_rng_init_phase1
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
     <platInit/>
     <persistRuntime/>
   </attribute>
   <!-- ********************************************************************* -->
-  <!-- TODO: add remaining nest MMIO BAR attributes required for IPL         -->
+  <attribute>
+    <id>ATTR_PROC_NX_RNG_BIST_THRESHOLD</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>BIST threshold attribute
+      creator: platform
+      consumer: p9_rng_init_phase1
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
   <!-- ********************************************************************* -->
 </attributes>