summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
diff options
context:
space:
mode:
authorChris Yan <fyan@us.ibm.com>2017-08-02 10:18:39 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-09-07 10:06:28 -0400
commitb60a858401ceff59d4a8daa05a13071dde886ddc (patch)
tree1ca2ce103d04213a131c43c7bee05ec630a2733a /src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
parent3078310870af66e14cc5775680cad4c5c4a2be78 (diff)
downloadtalos-hostboot-b60a858401ceff59d4a8daa05a13071dde886ddc.tar.gz
talos-hostboot-b60a858401ceff59d4a8daa05a13071dde886ddc.zip
ZZ VPD Pass 4 Board Update
- Split both ZZ and ZZ_lab folder trees - Update ZZ VPD files with new MR and MT settings - Update README.md - Update gen_vpd.pl - Introduce BIAS_TRIM attribute - Add to hb_temp_defaults.xml - Added enums for ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS - Modify DQ Map for port swizzling - Typo Fixes - Added previousLayoutValue identifier - MR swap mcs 2 and 3 - New TSYS values Change-Id: I71f007298853658338a9b25fd8592520c6408b1c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44100 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: FEIHONG YAN <fyan@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: FEIHONG YAN <fyan@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44189 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml')
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml181
1 files changed, 90 insertions, 91 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
index ff39283f8..32785aade 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
@@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
-<!-- Contributors Listed Below - COPYRIGHT 2016 -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
@@ -117,6 +117,21 @@
</attribute>
<attribute>
+ <id>ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET</id>
+ <targetType>TARGET_TYPE_MCS</targetType>
+ <description>
+ Default value for 2N Mode from Signal Integrity.
+ 0x01 = 1N Mode , 0x02 = 2N Mode
+ </description>
+ <initToZero></initToZero>
+ <valueType>uint8</valueType>
+ <writeable/>
+ <mssBlobStart>98</mssBlobStart>
+ <mssBlobLength>1</mssBlobLength>
+ <mssAccessorName>vpd_mr_mc_2n_mode_autoset</mssAccessorName>
+ </attribute>
+
+ <attribute>
<id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
@@ -469,178 +484,178 @@
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>56</mssBlobStart>
+ <mssBlobStart>64</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkp</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>58</mssBlobStart>
+ <mssBlobStart>66</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkn</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>60</mssBlobStart>
+ <mssBlobStart>68</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkp</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>62</mssBlobStart>
+ <mssBlobStart>70</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkn</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>64</mssBlobStart>
+ <mssBlobStart>72</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>66</mssBlobStart>
+ <mssBlobStart>74</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>68</mssBlobStart>
+ <mssBlobStart>76</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>70</mssBlobStart>
+ <mssBlobStart>82</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>72</mssBlobStart>
+ <mssBlobStart>84</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>74</mssBlobStart>
+ <mssBlobStart>90</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>76</mssBlobStart>
+ <mssBlobStart>92</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
<array>2</array>
</attribute>
@@ -677,7 +692,7 @@
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
@@ -686,14 +701,14 @@
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>82</mssBlobStart>
+ <mssBlobStart>86</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
@@ -702,125 +717,109 @@
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>84</mssBlobStart>
+ <mssBlobStart>88</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>86</mssBlobStart>
+ <mssBlobStart>94</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>88</mssBlobStart>
+ <mssBlobStart>96</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>90</mssBlobStart>
+ <mssBlobStart>58</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkn</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>92</mssBlobStart>
+ <mssBlobStart>56</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkp</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>94</mssBlobStart>
+ <mssBlobStart>62</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkn</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id>
+ <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+ Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
<writeable/>
<mssUnits>tick</mssUnits>
- <mssBlobStart>96</mssBlobStart>
+ <mssBlobStart>60</mssBlobStart>
<mssBlobLength>2</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
+ <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkp</mssAccessorName>
<array>2</array>
</attribute>
<attribute>
- <id>ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET</id>
- <targetType>TARGET_TYPE_MCS</targetType>
- <description>
- Default value for 2N Mode from Signal Integrity.
- 0x01 = 1N Mode , 0x02 = 2N Mode
- </description>
- <initToZero></initToZero>
- <valueType>uint8</valueType>
- <writeable/>
- <mssUnits></mssUnits>
- <mssBlobStart>98</mssBlobStart>
- <mssBlobLength>1</mssBlobLength>
- <mssAccessorName>vpd_mr_mc_2n_mode_autoset</mssAccessorName>
- </attribute>
-
- <attribute>
<id>ATTR_MSS_VPD_MR_TSYS_ADR</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
OpenPOWER on IntegriCloud