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author | Stephen Glancy <sglancy@us.ibm.com> | 2016-10-11 20:54:09 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-10-31 10:36:30 -0400 |
commit | c7cf0b2d56200537be4227b246fa5c4754cc7306 (patch) | |
tree | 1d00ece50c9f5a6e582e431ebc2e1b174edbb319 /src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | |
parent | a0575efc0dae3b41ee95e55d5a5e7acb12418c90 (diff) | |
download | talos-hostboot-c7cf0b2d56200537be4227b246fa5c4754cc7306.tar.gz talos-hostboot-c7cf0b2d56200537be4227b246fa5c4754cc7306.zip |
Fixed CL and timing bugs, unit test augmentations
Fix 3DS timing params for SLR and DLR and add unit tests.
Fix CL setting for non-configured ports and add unit CL tests
Fixed SPD timing errors, CL, MR, and ddr_phy UT bugs
Change-Id: Icc7efcc6f5a01ceee168a10ca8236cb656ba013c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31066
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31484
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml')
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 45 |
1 files changed, 36 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 8d5776543..b0353804e 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -2865,7 +2865,14 @@ <id>ATTR_EFF_DRAM_TREFI</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Average Refresh Interval (tREFI) in nck (number of clock cycles). + Average Refresh Interval (tREFI) + in nck (number of clock cycles). + This depends on MRW attribute that selects fine refresh mode (x1, x2, x4). + From DDR4 spec (79-4A). + + For 3DS, the tREFI time to the same logical rank is defined as + tRFC_slr1, tRFC_slr2, or tRFC_slr4. + creator: mss_eff_config consumer: various firmware notes: none @@ -2881,14 +2888,14 @@ <attribute> <id>ATTR_EFF_DRAM_TRTP</id> - <!-- Not an SPD byte - how to find this?? -AM --> <targetType>TARGET_TYPE_MCS</targetType> <description> - Internal Read to Precharge Delay. - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - consumer: various - firmware notes: none + Internal Read to Precharge Delay. + From the DDR4 spec (79-4A). + Each memory channel will have a value. + creator: mss_eff_cnfg_timing + consumer: various + firmware notes: none </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -2901,9 +2908,9 @@ <id>ATTR_EFF_DRAM_TRFC_DLR</id> <targetType>TARGET_TYPE_MCS</targetType> <description> - Minimum Refresh Recovery Delay Time + Minimum Refresh Recovery Delay Time (different logical ranks) in nck (number of clock cyles). - Selected tRFC value (tRFC_dl1, tRFC_dl2, or tRFC_dl4) + Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4) depends on MRW attribute that selects fine refresh mode (x1, x2, x4). For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr creator: eff_config @@ -2938,6 +2945,26 @@ </attribute> <attribute> + <id>ATTR_EFF_DRAM_TRRD_DLR</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Minimum Activate to Activate Delay Time (different logical ranks) + in nck (number of clock cycles). + For 3DS, The tRRD_S time to a different logical rank is defined as tRRD_dlr. + Each memory channel will have a value. + creator: eff_confg + consumer: various + firmware notes: none + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array> 2 </array> + <mssUnits> nck </mssUnits> + <mssAccessorName>eff_dram_trrd_dlr</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_EFF_DRAM_TXS</id> <targetType>TARGET_TYPE_MCS</targetType> <description> |