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| author | Brian Silver <bsilver@us.ibm.com> | 2016-03-14 18:38:08 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-18 09:34:24 -0400 |
| commit | bce6b464bf2fdbd15aa8302789194fc97a71dab1 (patch) | |
| tree | 3d80d773d5082211b8641ce7f6df7ad3ea612b63 /src/import/chips/p9/procedures/hwp | |
| parent | c2a41bf917d8d2e1e460c548317f86ef9760b71e (diff) | |
| download | talos-hostboot-bce6b464bf2fdbd15aa8302789194fc97a71dab1.tar.gz talos-hostboot-bce6b464bf2fdbd15aa8302789194fc97a71dab1.zip | |
Add ability to disable port fails for training
Change-Id: I265f7544b117887090a49870efce4cd168025b32
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22006
Tested-by: Jenkins Server
Tested-by: Auto Mirror
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22007
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 3 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index fcf17386f..3e18ebd99 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -98,6 +98,9 @@ extern "C" // set it low here kind of like belt-and-suspenders. BRS FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW) ); + // Re-enable port fails. Turned off in draminit_training + FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ) ); + // Step Two.1: Check RCD protect time on RDIMM and LRDIMM // Step Two.2: Enable address inversion on each MBA for ALL CARDS diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index ec5914f17..e6ae327e3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -134,6 +134,10 @@ extern "C" FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, 0) ); FAPI_TRY( mss::putScom(p, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, 0) ); + // Disable port fails as it doesn't appear the MC handles initial cal timeouts + // correctly (cal_length.) BRS, see conversation with Brad Michael + FAPI_TRY( mss::change_port_fail_disable(p, mss::ON ) ); + // The following registers must be configured to the correct operating environment: // Unclear, can probably be 0's for sim BRS |
