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| author | Thi Tran <thi@us.ibm.com> | 2016-09-13 10:20:24 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-24 15:44:51 -0400 |
| commit | ae1e0735bb243904249a1555292ece14415d2b38 (patch) | |
| tree | adc55e50474ffbee58fb8e2f36e8d17c8f2327dd /src/import/chips/p9/procedures/hwp | |
| parent | c1550894d13ea148ce85b45248271b7176005a70 (diff) | |
| download | talos-hostboot-ae1e0735bb243904249a1555292ece14415d2b38.tar.gz talos-hostboot-ae1e0735bb243904249a1555292ece14415d2b38.zip | |
Setup ATTR_OBUS_RATIO_VALUE for SBE platform
Change-Id: Ib9db247cf20b084a0106dd7b65819060ea1fc2ca
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29568
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29579
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C index 6a5dd5ead..529b46c83 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C @@ -55,22 +55,25 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3, ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29, ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3, - ATTR_BOOT_FREQ_MULT_STARTBIT = 0, - ATTR_BOOT_FREQ_MULT_LENGTH = 16, - ATTR_CP_FILTER_BYPASS_BIT = 16, - ATTR_SS_FILTER_BYPASS_BIT = 17, - ATTR_IO_FILTER_BYPASS_BIT = 18, - ATTR_DPLL_BYPASS_BIT = 19, - ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT = 20, - ATTR_NEST_PLL_BUCKET_STARTBIT = 24, - ATTR_NEST_PLL_BUCKET_LENGTH = 8, ATTR_CC_IPL_BIT = 0, ATTR_INIT_ALL_CORES_BIT = 1, ATTR_RISK_LEVEL_BIT = 2, ATTR_DISABLE_HBBL_VECTORS_BIT = 3, ATTR_MC_SYNC_MODE_BIT = 4, ATTR_PLL_MUX_STARTBIT = 12, - ATTR_PLL_MUX_LENGTH = 20 + ATTR_PLL_MUX_LENGTH = 20, + + // Scratch4 reg bit definitions + ATTR_BOOT_FREQ_MULT_STARTBIT = 0, + ATTR_BOOT_FREQ_MULT_LENGTH = 16, + ATTR_NEST_PLL_BUCKET_STARTBIT = 24, + ATTR_NEST_PLL_BUCKET_LENGTH = 8, + ATTR_CP_FILTER_BYPASS_BIT = 16, + ATTR_SS_FILTER_BYPASS_BIT = 17, + ATTR_IO_FILTER_BYPASS_BIT = 18, + ATTR_DPLL_BYPASS_BIT = 19, + ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT = 20, + ATTR_OBUS_RATIO_VALUE_BIT = 21, }; @@ -165,6 +168,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const uint8_t l_io_filter_bypass; uint8_t l_dpll_bypass; uint8_t l_nest_mem_x_o_pci_bypass; + uint8_t l_attr_obus_ratio = 0; FAPI_DBG("Reading Scratch_reg4"); //Getting SCRATCH_REGISTER_4 register value @@ -196,6 +200,11 @@ fapi2::ReturnCode p9_setup_sbe_config(const l_read_scratch_reg.writeBit<ATTR_DPLL_BYPASS_BIT>(l_dpll_bypass & 0x1); l_read_scratch_reg.writeBit<ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT>(l_nest_mem_x_o_pci_bypass & 0x1); + // Setting OBUS ratio + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, + l_attr_obus_ratio)); + l_read_scratch_reg.writeBit<ATTR_OBUS_RATIO_VALUE_BIT>(l_attr_obus_ratio & 0x1); + FAPI_DBG("Setting up value of Scratch_reg4"); //Setting SCRATCH_REGISTER_4 register value //CFAM.SCRATCH_REGISTER_4 = l_read_scratch_reg |
