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| author | Greg Still <stillgs@us.ibm.com> | 2017-08-24 13:34:06 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-09-06 16:06:24 -0400 |
| commit | 77e0173353795686ecf4c311f9bd79ddb74ca137 (patch) | |
| tree | 0a0871c3cf467677066bc01001d1844be6021f01 /src/import/chips/p9/procedures/hwp | |
| parent | 21fc8a22550254563195fb2b233fcca77335baa6 (diff) | |
| download | talos-hostboot-77e0173353795686ecf4c311f9bd79ddb74ca137.tar.gz talos-hostboot-77e0173353795686ecf4c311f9bd79ddb74ca137.zip | |
PM: Add atrribute control to SGPE for Core Periodic Quiesce
- Added SGPE header bit defintion
- Hcode image build update to read attr and set header bit
- Moved bit mask to using BIT macro for better readability
Change-Id: Ie8f245bf3abd0f5c4dce994f81ea1b002feade00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45124
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45179
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
3 files changed, 31 insertions, 12 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H index 05fc2fa21..1f8b72590 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -93,9 +93,12 @@ //------------------------- // Constants //------------------------- - +#ifndef __PPE_PLAT +#ifdef __cplusplus namespace p9hcd { +#endif +#endif // Bit masks used by CME hcode enum P9_HCD_CME_CORE_MASKS @@ -271,8 +274,11 @@ enum SICR_DEFS PCBMUX_REQ_C1 = 11 }; +#ifndef __PPE_PLAT +#ifdef __cplusplus } // END OF NAMESPACE p9hcd - +#endif +#endif #define P9_HCD_SCAN_FUNC_REPEAT 1 #define P9_HCD_SCAN_GPTR_REPEAT 1 diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 6e3b54d49..f3b1fcf9a 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -221,16 +221,17 @@ HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) HCD_CONST(SGPE_BUILD_VER_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_VER_BYTE)) -HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) -HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) -HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) -HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) -HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS, 0x08000000) -HCD_CONST(SGPE_VDM_ENABLE_BIT_POS, 0x04000000) -HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS, 0x02000000) -HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS, 0x00004000) -HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS, 0x00002000) -HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS, 0x00001000) +HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000) +HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000) +HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000) +HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) +HCD_CONST(SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS, 0x08000000) +HCD_CONST(SGPE_VDM_ENABLE_BIT_POS, 0x04000000) +HCD_CONST(SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS, 0x02000000) +HCD_CONST(SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS, 0x01000000) +HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS, 0x00004000) +HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS, 0x00002000) +HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS, 0x00001000) ///24x7 HCD_CONST(QPMR_AUX_OFFSET, (512 * ONE_KB)) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 274c1660b..590ca568d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -936,6 +936,18 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO FAPI_DBG("Cache DC Adjust Disabled : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE"); + + if( attrVal ) + { + sgpeFlag |= SGPE_CORE_PERIODIC_QUIESCE_DISABLE_POS; + } + + FAPI_DBG("Core Periodic Quiesce Disabled: %s", attrVal ? "TRUE" : "FALSE" ); + // Set PGPE Header Flags from Attributes FAPI_DBG(" -------------------- PGPE Flags -----------------"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE, |
